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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Konrad Schwarz <konrad.schwarz@siemens.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Ralf Ramsauer <ralf.ramsauer@oth-regensburg.de>,
	qemu-devel@nongnu.org
Subject: Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver
Date: Wed, 05 Jan 2022 18:43:32 +0000	[thread overview]
Message-ID: <874k6ij9z4.fsf@linaro.org> (raw)
In-Reply-To: <79194a3cf9e3bd1df41401eeee901055b8702c7b.1641309725.git.konrad.schwarz@siemens.com>


Konrad Schwarz <konrad.schwarz@siemens.com> writes:

> GDB target descriptions support typed registers;
> such that `info register X' displays not only the hex value of
> register `X', but also the individual bitfields the register
> comprises (if any), using textual labels if possible.
>
> This patch includes type information for GDB for
> a large subset of the RISC-V Control and Status Registers (CSRs).
>
> Signed-off-by: Konrad Schwarz <konrad.schwarz@siemens.com>
<snip>

Not withstanding my general comments (wish) to eventually get rid of
per-arch XML generation:

>  static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
>  {
>      RISCVCPU *cpu = RISCV_CPU(cs);
> @@ -163,21 +167,33 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
>      riscv_csr_predicate_fn predicate;
>      int bitsize = 16 << env->misa_mxl_max;
>      int i;
> +    riscv_csr_operations *csr_op;
> +    struct riscv_gdb_csr_tg const *csr_tg;
>  
>      g_string_printf(s, "<?xml version=\"1.0\"?>");
>      g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
>      g_string_append_printf(s, "<feature>      name=\"org.gnu.gdb.riscv.csr\">");

With these changes does it still match the org.gnu.gdb.riscv.csr
register description in gdb? Previously for custom XML I've used the
org.qemu.ARCH.REGS form to distinguish between something GDB expects and
something we invented (changed since 797920b952ea).

>  
> -    for (i = 0; i < CSR_TABLE_SIZE; i++) {
> -        predicate = csr_ops[i].predicate;
> +    g_string_append(s, riscv_gdb_csr_types);
> +
> +    for (i = 0, csr_op = csr_ops, csr_tg = riscv_gdb_csr_type_group;
> +            i < CSR_TABLE_SIZE; ++csr_op, ++csr_tg, ++i) {
> +        predicate = csr_op->predicate;
>          if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
> -            if (csr_ops[i].name) {
> -                g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
> +            if (csr_op->name) {
> +                g_string_append_printf(s, "<reg name=\"%s\"", csr_op->name);
>              } else {
>                  g_string_append_printf(s, "<reg name=\"csr%03x\"", i);
>              }
>              g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
> -            g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i);
> +            g_string_append_printf(s, " regnum=\"%d\"", base_reg + i);
> +            if (csr_tg->gdb_type) {
> +                g_string_append_printf(s, " type=\"%s\"", csr_tg->gdb_type);
> +            }
> +            if (csr_tg->gdb_group) {
> +                g_string_append_printf(s, " group=\"%s\"", csr_tg->gdb_group);
> +            }
> +            g_string_append(s, " />\n");
>          }
>      }
<snip>

-- 
Alex Bennée


  parent reply	other threads:[~2022-01-05 18:53 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-02 16:06 [PATCH v1 0/5] Improve RISC-V debugging support Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 1/5] RISC-V: larger and more consistent register set for 'info registers' Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 2/5] RISC-V: monitor's print register functionality Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 4/5] RISC-V: Typed CSRs in gdbserver Konrad Schwarz
2022-01-03 12:54   ` Ralf Ramsauer
2022-01-04 15:51     ` [PATCH v2 0/5] Improve RISC-V debugging support Konrad Schwarz
2022-01-04 15:51       ` [PATCH v2 1/5] RISC-V: larger and more consistent register set for 'info registers' Konrad Schwarz
2022-01-04 20:57         ` Richard Henderson
2022-01-05 12:38           ` Schwarz, Konrad
2022-01-05 18:21             ` Alex Bennée
2022-01-04 15:51       ` [PATCH v2 2/5] RISC-V: monitor's print register functionality Konrad Schwarz
2022-01-04 15:51       ` [PATCH v2 3/5] RISC-V: 'info gmem' to show hypervisor guest -> physical address translations Konrad Schwarz
2022-01-04 22:03         ` Alistair Francis
2022-01-05 13:09           ` Schwarz, Konrad
2022-01-04 15:51       ` [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver Konrad Schwarz
2022-01-04 22:11         ` Alistair Francis
2022-01-05 13:25           ` Schwarz, Konrad
2022-01-04 23:01         ` Richard Henderson
2022-01-05 14:04           ` Schwarz, Konrad
2022-01-05 20:20             ` Richard Henderson
2022-01-05 18:43         ` Alex Bennée [this message]
2022-01-05 19:24           ` Schwarz, Konrad
2022-01-05 19:34             ` Alex Bennée
2022-01-04 15:51       ` [PATCH v2 5/5] RISC-V: Add `v' (virtualization mode) bit to the `priv' virtual debug register Konrad Schwarz
2022-01-02 16:06 ` [PATCH v1 " Konrad Schwarz

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