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Wed, 5 Jan 2022 18:47:27 +0000 (GMT) References: <00a79b65-288f-f17c-abe4-fcfd3f7971fd@oth-regensburg.de> <79194a3cf9e3bd1df41401eeee901055b8702c7b.1641309725.git.konrad.schwarz@siemens.com> User-agent: mu4e 1.7.5; emacs 28.0.90 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Konrad Schwarz Subject: Re: [PATCH v2 4/5] RISC-V: Typed CSRs in gdbserver Date: Wed, 05 Jan 2022 18:43:32 +0000 In-reply-to: <79194a3cf9e3bd1df41401eeee901055b8702c7b.1641309725.git.konrad.schwarz@siemens.com> Message-ID: <874k6ij9z4.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::52d (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Palmer Dabbelt , Bin Meng , Alistair Francis , Ralf Ramsauer , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Konrad Schwarz writes: > GDB target descriptions support typed registers; > such that `info register X' displays not only the hex value of > register `X', but also the individual bitfields the register > comprises (if any), using textual labels if possible. > > This patch includes type information for GDB for > a large subset of the RISC-V Control and Status Registers (CSRs). > > Signed-off-by: Konrad Schwarz Not withstanding my general comments (wish) to eventually get rid of per-arch XML generation: > static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) > { > RISCVCPU *cpu =3D RISCV_CPU(cs); > @@ -163,21 +167,33 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, = int base_reg) > riscv_csr_predicate_fn predicate; > int bitsize =3D 16 << env->misa_mxl_max; > int i; > + riscv_csr_operations *csr_op; > + struct riscv_gdb_csr_tg const *csr_tg; >=20=20 > g_string_printf(s, ""); > g_string_append_printf(s, ""); > g_string_append_printf(s, " name=3D\"org.gnu.gdb.riscv= .csr\">"); With these changes does it still match the org.gnu.gdb.riscv.csr register description in gdb? Previously for custom XML I've used the org.qemu.ARCH.REGS form to distinguish between something GDB expects and something we invented (changed since 797920b952ea). >=20=20 > - for (i =3D 0; i < CSR_TABLE_SIZE; i++) { > - predicate =3D csr_ops[i].predicate; > + g_string_append(s, riscv_gdb_csr_types); > + > + for (i =3D 0, csr_op =3D csr_ops, csr_tg =3D riscv_gdb_csr_type_grou= p; > + i < CSR_TABLE_SIZE; ++csr_op, ++csr_tg, ++i) { > + predicate =3D csr_op->predicate; > if (predicate && (predicate(env, i) =3D=3D RISCV_EXCP_NONE)) { > - if (csr_ops[i].name) { > - g_string_append_printf(s, " + if (csr_op->name) { > + g_string_append_printf(s, "= name); > } else { > g_string_append_printf(s, " } > g_string_append_printf(s, " bitsize=3D\"%d\"", bitsize); > - g_string_append_printf(s, " regnum=3D\"%d\"/>", base_reg + i= ); > + g_string_append_printf(s, " regnum=3D\"%d\"", base_reg + i); > + if (csr_tg->gdb_type) { > + g_string_append_printf(s, " type=3D\"%s\"", csr_tg->gdb_= type); > + } > + if (csr_tg->gdb_group) { > + g_string_append_printf(s, " group=3D\"%s\"", csr_tg->gdb= _group); > + } > + g_string_append(s, " />\n"); > } > } --=20 Alex Benn=C3=A9e