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Thu, 29 Apr 2021 21:23:18 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 13TLNHsq22413812 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 29 Apr 2021 21:23:17 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C8036C6059; Thu, 29 Apr 2021 21:23:17 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F23B6C605F; Thu, 29 Apr 2021 21:23:16 +0000 (GMT) Received: from localhost (unknown [9.211.156.251]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTPS; Thu, 29 Apr 2021 21:23:16 +0000 (GMT) From: Fabiano Rosas To: "Bruno Larsen (billionai)" , qemu-devel@nongnu.org Subject: Re: [PATCH v2 7/7] target/ppc: isolated cpu init from translation logic In-Reply-To: <20210429162130.2412-8-bruno.larsen@eldorado.org.br> References: <20210429162130.2412-1-bruno.larsen@eldorado.org.br> <20210429162130.2412-8-bruno.larsen@eldorado.org.br> Date: Thu, 29 Apr 2021 18:23:14 -0300 Message-ID: <874kfo3hvh.fsf@linux.ibm.com> Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: LGvHTdR9WRWEVVOs8S_IuyZZTXM9Grd2 X-Proofpoint-ORIG-GUID: LGvHTdR9WRWEVVOs8S_IuyZZTXM9Grd2 X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-29_11:2021-04-28, 2021-04-29 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 spamscore=0 adultscore=0 mlxlogscore=999 suspectscore=0 malwarescore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2104290135 Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lucas.araujo@eldorado.org.br, luis.pires@eldorado.org.br, fernando.valle@eldorado.org.br, qemu-ppc@nongnu.org, "Bruno Larsen \(billionai\)" , matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" "Bruno Larsen (billionai)" writes: > finished isolation of CPU initialization logic from > translation logic. CPU initialization now only has common code > which may or may not call accelerator-specific code, as the > build options require, and is compiled separately. > > Signed-off-by: Bruno Larsen (billionai) > --- > target/ppc/{translate_init.c.inc => cpu_init.c} | 12 +++++++++++- > target/ppc/meson.build | 1 + > target/ppc/translate.c | 4 +++- > 3 files changed, 15 insertions(+), 2 deletions(-) > rename target/ppc/{translate_init.c.inc => cpu_init.c} (99%) > > diff --git a/target/ppc/translate_init.c.inc b/target/ppc/cpu_init.c > similarity index 99% > rename from target/ppc/translate_init.c.inc > rename to target/ppc/cpu_init.c > index b329e953cb..f0f8fc481e 100644 > --- a/target/ppc/translate_init.c.inc > +++ b/target/ppc/cpu_init.c > @@ -18,6 +18,7 @@ > * License along with this library; if not, see . > */ > > +#include "qemu/osdep.h" > #include "disas/dis-asm.h" > #include "exec/gdbstub.h" > #include "kvm_ppc.h" > @@ -42,6 +43,10 @@ > #include "fpu/softfloat.h" > #include "qapi/qapi-commands-machine-target.h" > > +#include "helper_regs.h" > +#include "internal.h" > +#include "spr_tcg.h" These two includes look like they belong in patch 3 and 4 respectively. And we probably want an #ifdef CONFIG_TCG around them. > + > /* #define PPC_DEBUG_SPR */ > /* #define USE_APPLE_GDB */ > > @@ -49,7 +54,12 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val) > { > /* Altivec always uses round-to-nearest */ > set_float_rounding_mode(float_round_nearest_even, &env->vec_status); > - helper_mtvscr(env, val); > + /* > + * This comment is here just so the project will build. > + * The current solution is in another patch and will be > + * added when we figure out an internal fork of qemu > + */ > + /* helper_mtvscr(env, val); */ > } > > #ifdef CONFIG_TCG > diff --git a/target/ppc/meson.build b/target/ppc/meson.build > index bbfef90e08..ad53629298 100644 > --- a/target/ppc/meson.build > +++ b/target/ppc/meson.build > @@ -2,6 +2,7 @@ ppc_ss = ss.source_set() > ppc_ss.add(files( > 'cpu-models.c', > 'cpu.c', > + 'cpu_init.c', > 'dfp_helper.c', > 'excp_helper.c', > 'fpu_helper.c', > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index a6e677fa6d..afb8a2aa27 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -38,6 +38,9 @@ > #include "qemu/atomic128.h" > #include "internal.h" > > +#include "qemu/qemu-print.h" > +#include "qapi/error.h" > +#include "internal.h" This one is already included. > > #define CPU_SINGLE_STEP 0x1 > #define CPU_BRANCH_STEP 0x2 > @@ -7595,7 +7598,6 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ > > #include "helper_regs.h" > #include "spr_tcg.c.inc" > -#include "translate_init.c.inc" > > /*****************************************************************************/ > /* Misc PowerPC helpers */