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Mon, 15 Feb 2021 04:02:15 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id o83sm25799934wme.37.2021.02.15.04.02.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Feb 2021 04:02:14 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9E0531FF7E; Mon, 15 Feb 2021 12:02:13 +0000 (GMT) References: <20210117164813.4101761-1-f4bug@amsat.org> <20210117164813.4101761-5-f4bug@amsat.org> <47f62c85-243c-ba70-56d6-0157afa5ae86@amsat.org> <35adfe42-6f89-1f48-7ed2-da1d2f4d7eb7@suse.de> User-agent: mu4e 1.5.8; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Claudio Fontana Subject: Re: [PATCH 4/6] accel/tcg: Declare missing cpu_loop_exit*() stubs Date: Mon, 15 Feb 2021 12:01:02 +0000 In-reply-to: <35adfe42-6f89-1f48-7ed2-da1d2f4d7eb7@suse.de> Message-ID: <874kidv8sa.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Huacai Chen , Eduardo Habkost , Riku Voipio , Richard Henderson , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Claudio Fontana writes: > On 1/18/21 10:39 AM, Philippe Mathieu-Daud=C3=A9 wrote: >> On 1/18/21 10:29 AM, Claudio Fontana wrote: >>> On 1/17/21 5:48 PM, Philippe Mathieu-Daud=C3=A9 wrote: >>>> cpu_loop_exit*() functions are declared in accel/tcg/cpu-exec-common.c, >>>> and are not available when TCG accelerator is not built. Add stubs so >>>> linking without TCG succeed. >>> >>> The reason why stubs are needed here at all seems to be that that the c= ode >>> calling cpu_loop_exit is not refactored properly yet; >>=20 >> I agree ... >>=20 >>> if we look at the example of i386, after the refactoring moving tcg rel= ated code into target/i386/tcg/, >>> (and really even before that I think), >>> the code calling cpu_loop_exit is not built for non-TCG at all, and so = we don't need stubs. >>> >>> I am ok with this anyway, just wanted to convey that I think we should = look at stubs as a necessary evil until all code stops mixing tcg, kvm and = other accels... >>> >>> Thanks, >>> >>> Claudio >>> >>>> >>>> Problematic files: >>>> >>>> - hw/semihosting/console.c in qemu_semihosting_console_inc() >>>> - hw/ppc/spapr_hcall.c in h_confer() >>>> - hw/s390x/ipl.c in s390_ipl_reset_request() >>>> - hw/misc/mips_itu.c >>=20 >> ... but I have no clue how to refactore these, as they >> are used in both KVM and TCG. >>=20 >> How would you do? I'm stuck with the semihosting code >> dependency on ARM since 2 years... >>=20 >> Phil. >>=20 > > Just naively looking at this, qemu_semihosting_console_inc seems called o= nly by > do_arm_semihosting in target/arm/arm-semi.c, > > which in turn is called by linux-user (TCG), > > target/arm/m_helper.c in arm_v7m_cpu_do_interrupt(), > which I would assume is TCG only too, just waiting for the TCG/KVM refact= oring in ARM, which I would assume would make cpu_tcg.c TCG-only, > > target/arm/helper.c in handle_semihosting, which is already wrapped in #i= fdef CONFIG_TCG and is commented with: > > " > * We only see semihosting exceptions in TCG only as they are not=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 > * trapped to the hypervisor in KVM.=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20=20 > */ > " > > So am I wrong in my assumption that as soon as we are able to separate > TCG vs KVM in target/arm/ , the issue of hw/semihosting/console.c > would be solved? I think it is - certainly for ARM. I don't know if real RiscV HW can trap semihosting calls to the kernel/hypervisor. --=20 Alex Benn=C3=A9e