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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <rth@twiddle.net>
Cc: qemu-devel@nongnu.org, cota@braap.org
Subject: Re: [Qemu-devel] [PATCH v5 03/19] qemu/atomic: Loosen restrictions for 64-bit ILP32 hosts
Date: Thu, 27 Apr 2017 17:10:18 +0100	[thread overview]
Message-ID: <874lx996hh.fsf@linaro.org> (raw)
In-Reply-To: <20170427120006.20564-4-rth@twiddle.net>


Richard Henderson <rth@twiddle.net> writes:

> We need to coordinate with the TCG_OVERSIZED_GUEST test in cputlb.c,
> and allow 64-bit atomics even though sizeof(void *) == 4.

Hmm you say this here but we never actually do it. But the other changes
seem fine.

>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  include/qemu/atomic.h | 34 ++++++++++++++++++++++++++--------
>  1 file changed, 26 insertions(+), 8 deletions(-)
>
> diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
> index 878fa07..8a564e9 100644
> --- a/include/qemu/atomic.h
> +++ b/include/qemu/atomic.h
> @@ -88,6 +88,24 @@
>  #define smp_read_barrier_depends()   barrier()
>  #endif
>
> +/* Sanity check that the size of an atomic operation isn't "overly large".
> + * Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
> + * want to use them because we ought not need them, and this lets us do a
> + * bit of sanity checking that other 32-bit hosts might build.
> + *
> + * That said, 64-bit hosts running in ilp32 mode cannot use pointer size
> + * as the test; we need the full register size.
> + * ??? Testing TCG_TARGET_REG_BITS == 64 would exact, but we probably do
> + * not want to pull in everything else TCG related.
> + *
> + * Note that x32 is fully detected with __x64_64__ + _ILP32, and that for
> + * Sparc we always force the use of sparcv9 in configure.
> + */
> +#if defined(__x86_64__) || defined(__sparc__)
> +# define ATOMIC_REG_SIZE  8
> +#else
> +# define ATOMIC_REG_SIZE  sizeof(void *)
> +#endif
>
>  /* Weak atomic operations prevent the compiler moving other
>   * loads/stores past the atomic operation load/store. However there is
> @@ -104,7 +122,7 @@
>
>  #define atomic_read(ptr)                              \
>      ({                                                \
> -    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
> +    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
>      atomic_read__nocheck(ptr);                        \
>      })
>
> @@ -112,7 +130,7 @@
>      __atomic_store_n(ptr, i, __ATOMIC_RELAXED)
>
>  #define atomic_set(ptr, i)  do {                      \
> -    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
> +    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
>      atomic_set__nocheck(ptr, i);                      \
>  } while(0)
>
> @@ -130,27 +148,27 @@
>
>  #define atomic_rcu_read(ptr)                          \
>      ({                                                \
> -    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
> +    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
>      typeof_strip_qual(*ptr) _val;                     \
>      atomic_rcu_read__nocheck(ptr, &_val);             \
>      _val;                                             \
>      })
>
>  #define atomic_rcu_set(ptr, i) do {                   \
> -    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
> +    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
>      __atomic_store_n(ptr, i, __ATOMIC_RELEASE);       \
>  } while(0)
>
>  #define atomic_load_acquire(ptr)                        \
>      ({                                                  \
> -    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));   \
> +    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE);  \
>      typeof_strip_qual(*ptr) _val;                       \
>      __atomic_load(ptr, &_val, __ATOMIC_ACQUIRE);        \
>      _val;                                               \
>      })
>
>  #define atomic_store_release(ptr, i)  do {              \
> -    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));   \
> +    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE);  \
>      __atomic_store_n(ptr, i, __ATOMIC_RELEASE);         \
>  } while(0)
>
> @@ -162,7 +180,7 @@
>  })
>
>  #define atomic_xchg(ptr, i)    ({                           \
> -    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));       \
> +    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE);      \
>      atomic_xchg__nocheck(ptr, i);                           \
>  })
>
> @@ -175,7 +193,7 @@
>  })
>
>  #define atomic_cmpxchg(ptr, old, new)    ({                             \
> -    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));                   \
> +    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE);                  \
>      atomic_cmpxchg__nocheck(ptr, old, new);                             \
>  })


--
Alex Bennée

  reply	other threads:[~2017-04-27 16:09 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-27 11:59 [Qemu-devel] [PATCH v5 00/19] TCG cross-tb optimizations Richard Henderson
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 01/19] target/nios2: Fix 64-bit ilp32 compilation Richard Henderson
2017-04-27 16:03   ` Alex Bennée
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 02/19] tcg/sparc: Use the proper compilation flags for 32-bit Richard Henderson
2017-04-27 16:04   ` Alex Bennée
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 03/19] qemu/atomic: Loosen restrictions for 64-bit ILP32 hosts Richard Henderson
2017-04-27 16:10   ` Alex Bennée [this message]
2017-04-28  7:07     ` Richard Henderson
2017-04-28  7:47       ` Alex Bennée
2017-04-28  8:05         ` Richard Henderson
2017-04-28 10:25           ` Alex Bennée
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 04/19] exec-all: export tb_htable_lookup Richard Henderson
2017-04-27 16:10   ` Alex Bennée
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 05/19] tcg-runtime: add lookup_tb_ptr helper Richard Henderson
2017-04-28 10:29   ` Alex Bennée
2017-04-28 10:32     ` Richard Henderson
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 06/19] tcg: introduce goto_ptr opcode Richard Henderson
2017-04-28 10:32   ` Alex Bennée
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 07/19] tcg: export tcg_gen_lookup_and_goto_ptr Richard Henderson
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 08/19] target/arm: optimize cross-page direct jumps in softmmu Richard Henderson
2017-04-28 11:30   ` Alex Bennée
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 09/19] target/arm: optimize indirect branches Richard Henderson
2017-04-27 22:58   ` Emilio G. Cota
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 10/19] target/i386: introduce gen_jr helper to generate lookup_and_goto_ptr Richard Henderson
2017-04-28 16:50   ` Alex Bennée
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 11/19] target/i386: optimize cross-page direct jumps in softmmu Richard Henderson
2017-04-28 16:56   ` Alex Bennée
2017-04-29  9:14     ` Richard Henderson
2017-04-27 11:59 ` [Qemu-devel] [PATCH v5 12/19] target/i386: optimize indirect branches Richard Henderson
2017-04-28 16:58   ` Alex Bennée
2017-04-27 12:00 ` [Qemu-devel] [PATCH v5 13/19] tb-hash: improve tb_jmp_cache hash function in user mode Richard Henderson
2017-04-28 17:00   ` Alex Bennée
2017-04-28 17:44     ` Emilio G. Cota
2017-04-27 12:00 ` [Qemu-devel] [PATCH v5 14/19] target/alpha: Use tcg_gen_goto_ptr Richard Henderson
2017-04-28 17:10   ` Alex Bennée
2017-04-27 12:00 ` [Qemu-devel] [PATCH v5 15/19] tcg/i386: implement goto_ptr Richard Henderson
2017-04-27 12:00 ` [Qemu-devel] [PATCH v5 16/19] tcg/ppc: Implement goto_ptr Richard Henderson
2017-04-27 12:00 ` [Qemu-devel] [PATCH v5 17/19] tcg/aarch64: " Richard Henderson
2017-04-27 22:18   ` Emilio G. Cota
2017-04-27 12:00 ` [Qemu-devel] [PATCH v5 18/19] tcg/sparc: " Richard Henderson
2017-04-27 12:00 ` [Qemu-devel] [PATCH v5 19/19] tcg/s390: " Richard Henderson
2017-04-27 12:58 ` [Qemu-devel] [PATCH v5 00/19] TCG cross-tb optimizations no-reply
2017-04-28 19:17 ` [Qemu-devel] [PATCH v5+] " Emilio G. Cota
2017-04-28 19:17   ` [Qemu-devel] [PATCH v5 + 1/2] target/aarch64: optimize cross-page direct jumps in softmmu Emilio G. Cota
2017-04-28 19:22     ` Emilio G. Cota
2017-04-29 10:30       ` Richard Henderson
2017-05-01  2:10         ` Emilio G. Cota
2017-04-28 19:17   ` [Qemu-devel] [PATCH v5 + 2/2] target/aarch64: optimize indirect branches Emilio G. Cota
2017-04-28 21:19     ` Emilio G. Cota
2017-04-30  9:47     ` Richard Henderson
2017-04-30 10:17       ` Richard Henderson
2017-04-30 14:52 ` [Qemu-devel] [PATCH v5++] TCG cross-tb optimizations Aurelien Jarno
2017-04-30 14:52   ` [Qemu-devel] [PATCH v5++ 1/3] tcg/mips: implement goto_ptr Aurelien Jarno
2017-05-01 22:00     ` Philippe Mathieu-Daudé
2017-05-02 16:21     ` Richard Henderson
2017-05-02 19:38       ` Aurelien Jarno
2017-04-30 14:52   ` [Qemu-devel] [PATCH v5++ 2/3] target/mips: optimize cross-page direct jumps in softmmu Aurelien Jarno
2017-04-30 14:52   ` [Qemu-devel] [PATCH v5++ 3/3] target/mips: optimize indirect branches Aurelien Jarno

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