From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:54348)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <alex.bennee@linaro.org>) id 1YIdmQ-0002tW-O1
	for qemu-devel@nongnu.org; Tue, 03 Feb 2015 08:44:43 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <alex.bennee@linaro.org>) id 1YIdmL-0004Nh-QO
	for qemu-devel@nongnu.org; Tue, 03 Feb 2015 08:44:38 -0500
Received: from static.88-198-71-155.clients.your-server.de
	([88.198.71.155]:42525 helo=socrates.bennee.com)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <alex.bennee@linaro.org>) id 1YIdmL-0004NT-In
	for qemu-devel@nongnu.org; Tue, 03 Feb 2015 08:44:33 -0500
References: <1422456666-12270-1-git-send-email-libhu.so@gmail.com>
	<87h9va7vfh.fsf@linaro.org>
	<CAFEAcA84cqR2WEG=15SAF9PfbMn_QO_6QQCbrX1j0Q2qoZ4dhA@mail.gmail.com>
	<CAFEAcA8pzvqaO3wHG4udQXj8vpaSJD2D33-8==s_GqfDbx2A-g@mail.gmail.com>
From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <CAFEAcA8pzvqaO3wHG4udQXj8vpaSJD2D33-8==s_GqfDbx2A-g@mail.gmail.com>
Date: Tue, 03 Feb 2015 13:44:49 +0000
Message-ID: <874mr3xg6m.fsf@linaro.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Subject: Re: [Qemu-devel] [PATCH] FMULX should flushes operators to zero
	when FZ is set.
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Xiangyu Hu <libhu.so@gmail.com>, QEMU Developers <qemu-devel@nongnu.org>


Peter Maydell <peter.maydell@linaro.org> writes:

> On 28 January 2015 at 15:57, Peter Maydell <peter.maydell@linaro.org> wrote:
>> On 28 January 2015 at 15:54, Alex Bennée <alex.bennee@linaro.org> wrote:
>>> Do we have test cases that trip up here? It would be nice to include
>>> them in our testing as the random nature of RISU has obviously failed to
>>> trip up on this instruction.
>>
>> Risu would probably catch this if we generated and ran test cases
>> which set the FPSCR bits to something other than the default.
>
> This bug is indeed caught by the following risugen:
> ./risugen --numinsns 10000 --pattern "FMULX A64_V" --fpscr 0x01000000
> aarch64.risu FMULX_S3SAME_V_squash.out
>
> (that fpscr value being "set DZ, nothing else".)
>
> Alex, I don't suppose your automation of these tests makes
> it easy to do a complete extra run (or better, just of the
> Neon and FP insn tests) with different FPSCR flags?

I just need to add the additional test sequence and trace to the tarball
and the script should pick it up automatically.

>
> -- PMM

-- 
Alex Bennée