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Tue, 9 Dec 2025 16:33:17 +0000 (UTC) Received: from localhost (dhcp-192-223.str.redhat.com [10.33.192.223]) by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 3114D30001BE; Tue, 9 Dec 2025 16:33:15 +0000 (UTC) From: Cornelia Huck To: Eric Auger , eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, sebott@redhat.com Cc: maz@kernel.org Subject: Re: [PATCH 3/3] target/arm/cpu-sysregs.h.inc: Update with automatic generation In-Reply-To: <20251208163751.611186-4-eric.auger@redhat.com> Organization: "Red Hat GmbH, Sitz: Werner-von-Siemens-Ring 12, D-85630 Grasbrunn, Handelsregister: Amtsgericht =?utf-8?Q?M=C3=BCnchen=2C?= HRB 153243, =?utf-8?Q?Gesch=C3=A4ftsf=C3=BChrer=3A?= Ryan Barnhart, Charles Cachera, Avril Crosse O'Flaherty" References: <20251208163751.611186-1-eric.auger@redhat.com> <20251208163751.611186-4-eric.auger@redhat.com> User-Agent: Notmuch/0.39 (https://notmuchmail.org) Date: Tue, 09 Dec 2025 17:33:13 +0100 Message-ID: <875xafr4xi.fsf@redhat.com> MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass client-ip=170.10.133.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Dec 08 2025, Eric Auger wrote: > Generated definitions with scripts/update-aarch64-sysreg-code.py > based on "AARCHMRS containing the JSON files for Arm A-profile > architecture (2025-09)" Registers.json file. > > Signed-off-by: Eric Auger > --- > target/arm/cpu-sysregs.h.inc | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc > index 3c892c4f30..9bb27297b5 100644 > --- a/target/arm/cpu-sysregs.h.inc > +++ b/target/arm/cpu-sysregs.h.inc > @@ -1,17 +1,27 @@ > -/* SPDX-License-Identifier: GPL-2.0-or-later */ > +/* SPDX-License-Identifier: BSD-3-Clause */ > + > +/* This file is autogenerated by scripts/update-aarch64-sysreg-code.py */ > + > +DEF(AIDR_EL1, 3, 1, 0, 0, 7) AIDR_EL1 (and MIDR_EL1/REVIDR_EL1) are used by the (hopefully-soon-respun) writable id register series, so it's good that they do not need to be added by hand anymore :) > DEF(CLIDR_EL1, 3, 1, 0, 0, 1) > DEF(CTR_EL0, 3, 3, 0, 0, 1) > +DEF(DCZID_EL0, 3, 3, 0, 0, 7) Also see https://lore.kernel.org/qemu-devel/20251127170657.3335112-1-cohuck@redhat.com/T/#u > +DEF(GMID_EL1, 3, 1, 0, 0, 4) > DEF(ID_AA64AFR0_EL1, 3, 0, 0, 5, 4) > DEF(ID_AA64AFR1_EL1, 3, 0, 0, 5, 5) > DEF(ID_AA64DFR0_EL1, 3, 0, 0, 5, 0) > DEF(ID_AA64DFR1_EL1, 3, 0, 0, 5, 1) > +DEF(ID_AA64DFR2_EL1, 3, 0, 0, 5, 2) > +DEF(ID_AA64FPFR0_EL1, 3, 0, 0, 4, 7) > DEF(ID_AA64ISAR0_EL1, 3, 0, 0, 6, 0) > DEF(ID_AA64ISAR1_EL1, 3, 0, 0, 6, 1) > DEF(ID_AA64ISAR2_EL1, 3, 0, 0, 6, 2) > +DEF(ID_AA64ISAR3_EL1, 3, 0, 0, 6, 3) > DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) > DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) > DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) > DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) > +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) > DEF(ID_AA64PFR0_EL1, 3, 0, 0, 4, 0) > DEF(ID_AA64PFR1_EL1, 3, 0, 0, 4, 1) > DEF(ID_AA64PFR2_EL1, 3, 0, 0, 4, 2) > @@ -36,6 +46,10 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6) > DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) > DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) > DEF(ID_PFR2_EL1, 3, 0, 0, 3, 4) > +DEF(MIDR_EL1, 3, 0, 0, 0, 0) > +DEF(MPIDR_EL1, 3, 0, 0, 0, 5) I'm wondering if we need to add some handling for MPIDR_EL1. > DEF(MVFR0_EL1, 3, 0, 0, 3, 0) > DEF(MVFR1_EL1, 3, 0, 0, 3, 1) > DEF(MVFR2_EL1, 3, 0, 0, 3, 2) > +DEF(REVIDR_EL1, 3, 0, 0, 0, 6) > +DEF(SMIDR_EL1, 3, 1, 0, 0, 6) SMIDR_EL1 is const 0 in tcg, and KVM currently does not support SME. So I guess we should init the idreg to 0 for now?