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Mon, 16 Sep 2024 01:41:35 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id B58365F87D; Mon, 16 Sep 2024 09:41:34 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, Richard Henderson , devel@lists.libvirt.org, Thomas Huth , Mahmoud Mandour , Paolo Bonzini , David Hildenbrand , Ilya Leoshkevich , qemu-ppc@nongnu.org, Zhao Liu , Yanan Wang , Eduardo Habkost , qemu-s390x@nongnu.org, Alexandre Iooss , Pierrick Bouvier , Nicholas Piggin , Daniel Henrique Barboza , Marcel Apfelbaum Subject: Re: [PATCH 11/17] tests/tcg: only read/write 64 bit words on 64 bit systems In-Reply-To: ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Fri, 13 Sep 2024 22:15:40 +0200") References: <20240913172655.173873-1-alex.bennee@linaro.org> <20240913172655.173873-12-alex.bennee@linaro.org> User-Agent: mu4e 1.12.6; emacs 29.4 Date: Mon, 16 Sep 2024 09:41:34 +0100 Message-ID: <875xqwgfcx.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Philippe Mathieu-Daud=C3=A9 writes: > On 13/9/24 19:26, Alex Benn=C3=A9e wrote: >> While the compilers will generally happily synthesise a 64 bit value >> for you on 32 bit systems it doesn't exercise anything on QEMU. It >> also makes it hard to accurately compare the accesses to test_data >> when instrumenting. >> Message-Id: <20240910140733.4007719-21-alex.bennee@linaro.org> >> Reviewed-by: Pierrick Bouvier >> Signed-off-by: Alex Benn=C3=A9e >> --- >> tests/tcg/multiarch/system/memory.c | 26 +++++++++++++++++++------- >> 1 file changed, 19 insertions(+), 7 deletions(-) >> diff --git a/tests/tcg/multiarch/system/memory.c >> b/tests/tcg/multiarch/system/memory.c >> index 8f2371975d..680dd4800b 100644 >> --- a/tests/tcg/multiarch/system/memory.c >> +++ b/tests/tcg/multiarch/system/memory.c >> @@ -163,6 +163,7 @@ static void init_test_data_u32(int offset) >> ml_printf("done %d @ %p\n", i, ptr); >> } >> +#if __SIZEOF_POINTER__ =3D=3D 8 > >>=3D ? :) Ahh I was confused by the email quoting. Do we actually have any systems with bigger pointers or is this just for future proofing? > >> static void init_test_data_u64(int offset) >> { >> uint8_t count =3D 0; >> @@ -187,6 +188,7 @@ static void init_test_data_u64(int offset) >> } >> ml_printf("done %d @ %p\n", i, ptr); >> } >> +#endif >> static bool read_test_data_u16(int offset) >> { >> @@ -254,6 +256,7 @@ static bool read_test_data_u32(int offset) >> return true; >> } >> +#if __SIZEOF_POINTER__ =3D=3D 8 >> static bool read_test_data_u64(int offset) >> { >> uint64_t word, *ptr =3D (uint64_t *)&test_data[offset]; >> @@ -307,11 +310,16 @@ static bool read_test_data_u64(int offset) >> ml_printf("done %d @ %p\n", i, ptr); >> return true; >> } >> +#endif >> /* Read the test data and verify at various offsets */ >> -read_ufn read_ufns[] =3D { read_test_data_u16, >> - read_test_data_u32, >> - read_test_data_u64 }; >> +read_ufn read_ufns[] =3D { >> + read_test_data_u16, >> + read_test_data_u32, >> +#if __SIZEOF_POINTER__ =3D=3D 8 >> + read_test_data_u64 >> +#endif >> +}; >> bool do_unsigned_reads(int start_off) >> { >> @@ -476,10 +484,14 @@ bool do_signed_reads(bool neg_first) >> return ok; >> } >> -init_ufn init_ufns[] =3D { init_test_data_u8, >> - init_test_data_u16, >> - init_test_data_u32, >> - init_test_data_u64 }; >> +init_ufn init_ufns[] =3D { >> + init_test_data_u8, >> + init_test_data_u16, >> + init_test_data_u32, >> +#if __SIZEOF_POINTER__ =3D=3D 8 >> + init_test_data_u64 >> +#endif >> +}; >> int main(void) >> { --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro