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Mon, 12 Aug 2024 04:10:01 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id E903A5F8FE; Mon, 12 Aug 2024 12:10:00 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: Richard Henderson , qemu-devel@nongnu.org Subject: Re: [PULL 09/11] target/arm: add support for PMUv3 64-bit PMCCNTR in AArch32 mode In-Reply-To: (Peter Maydell's message of "Mon, 12 Aug 2024 10:39:36 +0100") References: <20240809180835.1243269-1-peter.maydell@linaro.org> <20240809180835.1243269-10-peter.maydell@linaro.org> <945e5e14-9a15-4dfc-856f-f3a7d401a5bc@linaro.org> Date: Mon, 12 Aug 2024 12:10:00 +0100 Message-ID: <875xs6atfb.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Peter Maydell writes: > On Sun, 11 Aug 2024 at 22:36, Richard Henderson > wrote: >> >> On 8/10/24 04:08, Peter Maydell wrote: >> > From: Alex Richardson >> > diff --git a/target/arm/helper.c b/target/arm/helper.c >> > index 8fb4b474e83..94900667c33 100644 >> > --- a/target/arm/helper.c >> > +++ b/target/arm/helper.c >> > @@ -5952,6 +5952,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { >> > .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, >> > .writefn =3D sdcr_write, >> > .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, >> > + { .name =3D "PMCCNTR", .state =3D ARM_CP_STATE_AA32, >> > + .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_64BIT, >> > + .cp =3D 15, .crm =3D 9, .opc1 =3D 0, >> > + .access =3D PL0_RW, .resetvalue =3D 0, .fgt =3D FGT_PMCCNTR_EL0, >> > + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, >> > + .accessfn =3D pmreg_access_ccntr }, >> > }; >> > >> > /* These are present only when EL1 supports AArch32 */ >> >> This fails testing: >> >> https://gitlab.com/qemu-project/qemu/-/jobs/7551982466 >> >> FAIL: duplicate register {'name': 'PMCCNTR', 'regnum': 96} vs {'name': '= PMCCNTR', >> 'regnum': 79} >> FAIL: counted all 219 registers in XML >> FAIL: PMCCNTR 96 =3D=3D 79 (xml) > > Hmm, not sure why that didn't get caught by my local testing > or by my gitlab run -- does it only get run on an aarch64 host? It will depend what your local GDB is like - a modern gdb-multiarch should be fine but we do test for a minimum version to be able to probe the supported architectures. > Anyway, the registers do architecturally have the same name > (they're the same register, just accessible via different > pathways). What is our practice for this? Do we just give > one of them a non-standard name? > > -- PMM --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro