From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1814DC67861 for ; Mon, 8 Apr 2024 08:57:40 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rtkoe-0001hE-GE; Mon, 08 Apr 2024 04:57:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rtkod-0001fi-UV for qemu-devel@nongnu.org; Mon, 08 Apr 2024 04:57:23 -0400 Received: from ik1-413-38519.vs.sakura.ne.jp ([153.127.30.23] helo=sakura.ysato.name) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rtkoc-0006JB-7n for qemu-devel@nongnu.org; Mon, 08 Apr 2024 04:57:23 -0400 Received: from SIOS1075.ysato.ml (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id DD6331C102D; Mon, 8 Apr 2024 17:57:20 +0900 (JST) Date: Mon, 08 Apr 2024 17:57:20 +0900 Message-ID: <875xwscjv3.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: Zack Buhman Cc: qemu-devel@nongnu.org Subject: Re: [PATCH] target/sh4: add missing CHECK_NOT_DELAY_SLOT In-Reply-To: <20240407150705.5965-1-zack@buhman.org> References: <20240407150705.5965-1-zack@buhman.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Received-SPF: softfail client-ip=153.127.30.23; envelope-from=ysato@users.sourceforge.jp; helo=sakura.ysato.name X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 08 Apr 2024 00:07:05 +0900, Zack Buhman wrote: > > CHECK_NOT_DELAY_SLOT is correctly applied to the branch-related > instructions, but not to the PC-relative mov* instructions. > > I verified the existence of an illegal slot exception on a SH7091 when > any of these instructions are attempted inside a delay slot. > > This also matches the behavior described in the SH-4 ISA manual. > > Signed-off-by: Zack Buhman > --- > target/sh4/translate.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/sh4/translate.c b/target/sh4/translate.c > index 6643c14dde..ebb6c901bf 100644 > --- a/target/sh4/translate.c > +++ b/target/sh4/translate.c > @@ -523,6 +523,7 @@ static void _decode_opc(DisasContext * ctx) > tcg_gen_movi_i32(REG(B11_8), B7_0s); > return; > case 0x9000: /* mov.w @(disp,PC),Rn */ > + CHECK_NOT_DELAY_SLOT > { > TCGv addr = tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * 2); > tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, > @@ -530,6 +531,7 @@ static void _decode_opc(DisasContext * ctx) > } > return; > case 0xd000: /* mov.l @(disp,PC),Rn */ > + CHECK_NOT_DELAY_SLOT > { > TCGv addr = tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3); > tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, > @@ -1236,6 +1238,7 @@ static void _decode_opc(DisasContext * ctx) > } > return; > case 0xc700: /* mova @(disp,PC),R0 */ > + CHECK_NOT_DELAY_SLOT > tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffffffc) + > 4 + B7_0 * 4) & ~3); > return; > -- > 2.41.0 > That's what the documentation said. > If a PC-relative load instruction is executed in a delay slot, > an illegal slot instruction exception will be generated. Reviewed-by: Yoshinori Sato -- Yosinori Sato