From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 051CDCDB47E for ; Thu, 19 Oct 2023 02:10:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtIU0-0002fe-Ia; Wed, 18 Oct 2023 22:09:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtITx-0002e3-Tt for qemu-devel@nongnu.org; Wed, 18 Oct 2023 22:09:53 -0400 Received: from hsmtpd-def.xspmail.jp ([2001:240:bb81:94:202:238:198:240]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtITu-0007y9-Sd for qemu-devel@nongnu.org; Wed, 18 Oct 2023 22:09:53 -0400 X-Country-Code: JP Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by hsmtpd-out-2.asahinet.cluster.xspmail.jp (Halon) with ESMTPA id 6a2ea581-6fb8-41dc-99d5-2e253b2bdcc2; Thu, 19 Oct 2023 11:03:41 +0900 (JST) Received: from SIOS1075.ysato.ml (al128006.dynamic.ppp.asahi-net.or.jp [111.234.128.6]) by sakura.ysato.name (Postfix) with ESMTPSA id 7C1F01C0037; Thu, 19 Oct 2023 11:03:39 +0900 (JST) Date: Thu, 19 Oct 2023 11:03:39 +0900 Message-ID: <875y338j2c.wl-ysato@users.sourceforge.jp> From: Yoshinori Sato To: Geert Uytterhoeven Cc: Guenter Roeck , qemu-devel@nongnu.org, linux-sh@vger.kernel.org Subject: Re: [PATCH RFC] hw/sh4/sh7750: Add STBCR/STBCR2 register support In-Reply-To: <20231018124023.2927710-1-geert+renesas@glider.be> References: <20231018124023.2927710-1-geert+renesas@glider.be> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Received-SPF: softfail client-ip=2001:240:bb81:94:202:238:198:240; envelope-from=ysato@users.sourceforge.jp; helo=hsmtpd-def.xspmail.jp X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, 18 Oct 2023 21:40:23 +0900, Geert Uytterhoeven wrote: > > The new Linux SH7750 clock driver uses the registers for power-down > mode control, causing a crash: > > byte read to SH7750_STBCR_A7 (0x000000001fc00004) not supported > Aborted (core dumped) > > Fix this by adding support for the Standby Control Registers STBCR and > STBCR2. FRQCR is also not returning the correct value, so it needs to be fixed. Here are my changes. https://gitlab.com/yoshinori.sato/qemu.git It include. - Minimal CPG support. - DT support - Add target LANDISK. > Signed-off-by: Geert Uytterhoeven > --- > [RFC PATCH v3 12/35] drivers/clk/renesas: clk-sh7750.c SH7750/7751 CPG driver. > https://lore.kernel.org/all/a772e1b6de89af22057d3af31cc03dcad7964fc7.1697199949.git.ysato@users.sourceforge.jp > > Accesses to CLKSTP00 and CLKSTCLK00 (0xfe0a0000/0x1e0a0000 and > 0xfe0a0008/0x1e0a0008) don't seem to cause any issues, although I can't > see immediately where they are handled? > > --- > hw/sh4/sh7750.c | 23 +++++++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) > > diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c > index ebe0fd96d94ca17b..deeb83b4540bbf2b 100644 > --- a/hw/sh4/sh7750.c > +++ b/hw/sh4/sh7750.c > @@ -59,6 +59,9 @@ typedef struct SH7750State { > uint16_t bcr3; > uint32_t bcr4; > uint16_t rfcr; > + /* Power-Down Modes */ > + uint8_t stbcr; > + uint8_t stbcr2; > /* PCMCIA controller */ > uint16_t pcr; > /* IO ports */ > @@ -219,7 +222,13 @@ static void ignore_access(const char *kind, hwaddr addr) > > static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr) > { > + SH7750State *s = opaque; > + > switch (addr) { > + case SH7750_STBCR_A7: > + return s->stbcr; > + case SH7750_STBCR2_A7: > + return s->stbcr2; > default: > error_access("byte read", addr); > abort(); > @@ -318,14 +327,24 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) > static void sh7750_mem_writeb(void *opaque, hwaddr addr, > uint32_t mem_value) > { > + SH7750State *s = opaque; > > if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { > ignore_access("byte write", addr); > return; > } > > - error_access("byte write", addr); > - abort(); > + switch (addr) { > + case SH7750_STBCR_A7: > + s->stbcr = mem_value; > + return; > + case SH7750_STBCR2_A7: > + s->stbcr2 = mem_value; > + return; > + default: > + error_access("byte write", addr); > + abort(); > + } > } > > static void sh7750_mem_writew(void *opaque, hwaddr addr, > -- > 2.34.1 > -- Yosinori Sato