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Mon, 10 Jan 2022 19:00:55 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 54953AC07B; Mon, 10 Jan 2022 19:00:54 +0000 (GMT) Received: from localhost (unknown [9.211.79.41]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTPS; Mon, 10 Jan 2022 19:00:53 +0000 (GMT) From: Fabiano Rosas To: BALATON Zoltan Subject: Re: [PATCH 4/8] squash target/ppc: Introduce powerpc_excp_40x In-Reply-To: <17495cce-79f1-1483-aab3-86ffcde7492e@eik.bme.hu> References: <20220110181546.4131853-1-farosas@linux.ibm.com> <20220110181546.4131853-5-farosas@linux.ibm.com> <17495cce-79f1-1483-aab3-86ffcde7492e@eik.bme.hu> Date: Mon, 10 Jan 2022 16:00:50 -0300 Message-ID: <875yqra00t.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: fLnMSIq_-RMoxiaqshta-pSPJ2Rfu29D X-Proofpoint-ORIG-GUID: AdmhHOGHF0of2t317RoI4UmaK3f6-4Ih X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-10_08,2022-01-10_02,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 priorityscore=1501 bulkscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=739 mlxscore=0 spamscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201100130 Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" BALATON Zoltan writes: > On Mon, 10 Jan 2022, Fabiano Rosas wrote: >> Introduce a new exception dispatcher for 40x CPUs. >> >> Differences from the generic powerpc_excp code: >> >> - Not BookE, so some MSR bits are cleared at interrupt dispatch; >> - No MSR_HV or MSR_LE; >> - No power saving states; >> - No Hypervisor Emulation Assistance; >> - Not 64 bits; >> - No System call vectored; >> - No Interrupts Little Endian; >> - No Alternate Interrupt Location. >> >> Exceptions used: >> >> POWERPC_EXCP_ALIGN >> POWERPC_EXCP_APU >> POWERPC_EXCP_CRITICAL >> POWERPC_EXCP_DEBUG >> POWERPC_EXCP_DSI >> POWERPC_EXCP_DTLB >> POWERPC_EXCP_EXTERNAL >> POWERPC_EXCP_FIT >> POWERPC_EXCP_FPU >> POWERPC_EXCP_ISI >> POWERPC_EXCP_ITLB >> POWERPC_EXCP_MCHECK >> POWERPC_EXCP_PIT >> POWERPC_EXCP_PROGRAM >> POWERPC_EXCP_SYSCALL >> POWERPC_EXCP_WDT >> >> Signed-off-by: Fabiano Rosas >> --- >> target/ppc/excp_helper.c | 165 +++------------------------------------ >> 1 file changed, 13 insertions(+), 152 deletions(-) >> >> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c >> index 12ab5e1b34..1d997c4d6b 100644 >> --- a/target/ppc/excp_helper.c >> +++ b/target/ppc/excp_helper.c >> @@ -409,54 +409,18 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) >> excp, env->error_code); >> >> /* new srr1 value excluding must-be-zero bits */ >> - if (excp_model == POWERPC_EXCP_BOOKE) { >> - msr = env->msr; >> - } else { >> - msr = env->msr & ~0x783f0000ULL; >> - } >> + msr = env->msr & ~0x783f0000ULL; >> >> /* >> - * new interrupt handler msr preserves existing HV and ME unless >> - * explicitly overriden >> + * new interrupt handler msr preserves existing ME unless >> + * explicitly overriden. >> */ >> - new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); >> + new_msr = env->msr & (((target_ulong)1 << MSR_ME)); >> >> /* target registers */ >> srr0 = SPR_SRR0; >> srr1 = SPR_SRR1; >> >> - /* >> - * check for special resume at 0x100 from doze/nap/sleep/winkle on >> - * P7/P8/P9 >> - */ >> - if (env->resume_as_sreset) { >> - excp = powerpc_reset_wakeup(cs, env, excp, &msr); >> - } >> - >> - /* >> - * Hypervisor emulation assistance interrupt only exists on server >> - * arch 2.05 server or later. We also don't want to generate it if >> - * we don't have HVB in msr_mask (PAPR mode). >> - */ >> - if (excp == POWERPC_EXCP_HV_EMU >> -#if defined(TARGET_PPC64) >> - && !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB)) >> -#endif /* defined(TARGET_PPC64) */ >> - >> - ) { >> - excp = POWERPC_EXCP_PROGRAM; >> - } >> - >> -#ifdef TARGET_PPC64 >> - /* >> - * SPEU and VPU share the same IVOR but they exist in different >> - * processors. SPEU is e500v1/2 only and VPU is e6500 only. >> - */ >> - if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) { >> - excp = POWERPC_EXCP_SPEU; >> - } >> -#endif >> - >> vector = env->excp_vectors[excp]; >> if (vector == (target_ulong)-1ULL) { >> cpu_abort(cs, "Raised an exception without defined vector %d\n", >> @@ -581,6 +545,11 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) >> */ >> env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; >> break; >> + case POWERPC_EXCP_HV_EMU: >> + /* >> + * Hypervisor emulation assistance interrupt only exists on server >> + * arch 2.05 server or later. >> + */ >> case POWERPC_EXCP_PROGRAM: /* Program exception */ >> switch (env->error_code & ~0xF) { >> case POWERPC_EXCP_FP: >> @@ -645,22 +614,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) >> new_msr |= (target_ulong)MSR_HVB; >> } >> break; >> - case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */ >> - lev = env->error_code; >> - dump_syscall(env); >> - env->nip += 4; >> - new_msr |= env->msr & ((target_ulong)1 << MSR_EE); >> - new_msr |= env->msr & ((target_ulong)1 << MSR_RI); >> - >> - vector += lev * 0x20; >> - >> - env->lr = env->nip; >> - env->ctr = msr; >> - break; >> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ >> case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ >> - case POWERPC_EXCP_DECR: /* Decrementer exception */ >> - break; > > Removing the break here makes FPU and APU fall through to FIT. Is that > intentional? No, that is a mistake indeed. Thanks.