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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org,
	david@gibson.dropbear.id.au, zhiwei_liu@c-sky.com,
	david@redhat.com
Subject: Re: [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm
Date: Mon, 20 Apr 2020 11:06:31 +0100	[thread overview]
Message-ID: <875zdufp3s.fsf@linaro.org> (raw)
In-Reply-To: <20200418150411.1831-3-richard.henderson@linaro.org>


Richard Henderson <richard.henderson@linaro.org> writes:

> The gen_gvec_dupi switch is unnecessarily with the new function.
> Replace it with a local gen_gvec_dup_imm that takes care of the
> register to offset conversion and length arguments.
>
> Drop zero_vec and use use gen_gvec_dup_imm with 0.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  target/s390x/translate_vx.inc.c | 41 +++++++--------------------------
>  1 file changed, 8 insertions(+), 33 deletions(-)
>
> diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
> index 24558cce80..12347f8a03 100644
> --- a/target/s390x/translate_vx.inc.c
> +++ b/target/s390x/translate_vx.inc.c
> @@ -231,8 +231,8 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
>  #define gen_gvec_mov(v1, v2) \
>      tcg_gen_gvec_mov(0, vec_full_reg_offset(v1), vec_full_reg_offset(v2), 16, \
>                       16)
> -#define gen_gvec_dup64i(v1, c) \
> -    tcg_gen_gvec_dup64i(vec_full_reg_offset(v1), 16, 16, c)
> +#define gen_gvec_dup_imm(es, v1, c) \
> +    tcg_gen_gvec_dup_imm(es, vec_full_reg_offset(v1), 16, 16, c);
>  #define gen_gvec_fn_2(fn, es, v1, v2) \
>      tcg_gen_gvec_##fn(es, vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
>                        16, 16)
> @@ -316,31 +316,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn, uint8_t d, uint8_t a,
>          tcg_temp_free_i64(cl);
>  }
>  
> -static void gen_gvec_dupi(uint8_t es, uint8_t reg, uint64_t c)
> -{
> -    switch (es) {
> -    case ES_8:
> -        tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, c);
> -        break;
> -    case ES_16:
> -        tcg_gen_gvec_dup16i(vec_full_reg_offset(reg), 16, 16, c);
> -        break;
> -    case ES_32:
> -        tcg_gen_gvec_dup32i(vec_full_reg_offset(reg), 16, 16, c);
> -        break;
> -    case ES_64:
> -        gen_gvec_dup64i(reg, c);
> -        break;
> -    default:
> -        g_assert_not_reached();
> -    }
> -}
> -
> -static void zero_vec(uint8_t reg)
> -{
> -    tcg_gen_gvec_dup8i(vec_full_reg_offset(reg), 16, 16, 0);
> -}
> -
>  static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 ah,
>                            uint64_t b)
>  {
> @@ -396,8 +371,8 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
>           * Masks for both 64 bit elements of the vector are the same.
>           * Trust tcg to produce a good constant loading.
>           */
> -        gen_gvec_dup64i(get_field(s, v1),
> -                        generate_byte_mask(i2 & 0xff));
> +        gen_gvec_dup_imm(ES_64, get_field(s, v1),
> +                         generate_byte_mask(i2 & 0xff));
>      } else {
>          TCGv_i64 t = tcg_temp_new_i64();
>  
> @@ -432,7 +407,7 @@ static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
>          }
>      }
>  
> -    gen_gvec_dupi(es, get_field(s, v1), mask);
> +    gen_gvec_dup_imm(es, get_field(s, v1), mask);
>      return DISAS_NEXT;
>  }
>  
> @@ -585,7 +560,7 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
>  
>      t = tcg_temp_new_i64();
>      tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
> -    zero_vec(get_field(s, v1));
> +    gen_gvec_dup_imm(es, get_field(s, v1), 0);
>      write_vec_element_i64(t, get_field(s, v1), enr, es);
>      tcg_temp_free_i64(t);
>      return DISAS_NEXT;
> @@ -892,7 +867,7 @@ static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
>          return DISAS_NORETURN;
>      }
>  
> -    gen_gvec_dupi(es, get_field(s, v1), data);
> +    gen_gvec_dup_imm(es, get_field(s, v1), data);
>      return DISAS_NEXT;
>  }
>  
> @@ -1372,7 +1347,7 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasOps *o)
>          read_vec_element_i32(tmp, get_field(s, v2), i, ES_32);
>          tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
>      }
> -    zero_vec(get_field(s, v1));
> +    gen_gvec_dup_imm(ES_32, get_field(s, v1), 0);
>      write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
>  
>      tcg_temp_free_i32(tmp);


-- 
Alex Bennée


  parent reply	other threads:[~2020-04-20 10:08 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-18 15:04 [PATCH 0/7] tcg: Clean up tcg_gen_gvec_dupi interface Richard Henderson
2020-04-18 15:04 ` [PATCH 1/7] tcg: Add tcg_gen_gvec_dup_imm Richard Henderson
2020-04-20  3:17   ` LIU Zhiwei
2020-04-20  7:29   ` David Hildenbrand
2020-04-20  9:43   ` Alex Bennée
2020-04-18 15:04 ` [PATCH 2/7] target/s390x: Use tcg_gen_gvec_dup_imm Richard Henderson
2020-04-20  7:29   ` David Hildenbrand
2020-04-20  9:46   ` Alex Bennée
2020-04-20 10:06   ` Alex Bennée [this message]
2020-04-18 15:04 ` [PATCH 3/7] target/ppc: " Richard Henderson
2020-04-20  3:41   ` David Gibson
2020-04-20 10:34   ` Alex Bennée
2020-04-21 17:50     ` Richard Henderson
2020-04-22  7:58       ` David Gibson
2020-04-18 15:04 ` [PATCH 4/7] target/arm: " Richard Henderson
2020-04-20 13:24   ` Alex Bennée
2020-04-18 15:04 ` [PATCH 5/7] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications Richard Henderson
2020-04-20  4:30   ` LIU Zhiwei
2020-04-20 13:32   ` Alex Bennée
2020-04-18 15:04 ` [PATCH 6/7] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i Richard Henderson
2020-04-20  4:33   ` LIU Zhiwei
2020-04-20  7:29   ` David Hildenbrand
2020-04-20 13:32   ` Alex Bennée
2020-04-18 15:04 ` [PATCH 7/7] tcg: Add tcg_gen_gvec_dup_tl Richard Henderson
2020-04-20  4:42   ` LIU Zhiwei
2020-04-20  7:30   ` David Hildenbrand
2020-04-20 14:52     ` Richard Henderson
2020-04-20 14:55       ` David Hildenbrand
2020-04-20 13:32   ` Alex Bennée

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