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X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > Continue setting, but not relying upon, env->hflags. > > Signed-off-by: Richard Henderson > --- > target/arm/op_helper.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c > index ccc2cecb46..b529d6c1bf 100644 > --- a/target/arm/op_helper.c > +++ b/target/arm/op_helper.c > @@ -224,6 +224,7 @@ uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x,= uint32_t shift) > void HELPER(setend)(CPUARMState *env) > { > env->uncached_cpsr ^=3D CPSR_E; > + arm_rebuild_hflags(env); > } > > /* Function checks whether WFx (WFI/WFE) instructions are set up to be t= rapped. > @@ -387,6 +388,8 @@ uint32_t HELPER(cpsr_read)(CPUARMState *env) > void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) > { > cpsr_write(env, val, mask, CPSRWriteByInstr); > + /* TODO: Not all cpsr bits are relevant to hflags. */ Do you mean by this we could check which bits changed and avoid a re-compute if we wanted to? Is it likely to be anything other than the SS_ACTIVE bit? > + arm_rebuild_hflags(env); > } > > /* Write the CPSR for a 32-bit exception return */ Anyway: Reviewed-by: Alex Benn=C3=A9e -- Alex Benn=C3=A9e