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X-Received-From: 2a00:1450:4864:20::341 Subject: Re: [Qemu-devel] [PATCH for-4.2 09/24] target/arm: Add TTBR1_EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > At the same time, add writefn to TTBR0_EL2 and TCR_EL2. > > Signed-off-by: Richard Henderson > --- > target/arm/helper.c | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d1bf31ab74..da2e0627b2 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3449,6 +3449,15 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, = const ARMCPRegInfo *ri, > } > } > > +static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo= *ri, > + uint64_t value) > +{ > + raw_write(env, ri, value); I wonder if the bellow would be better merged with: target/arm: Install asids for E2&0 translation regime And the commit message amended to say something like: "later patches will potentially update the asid" > + if (arm_hcr_el2_eff(env) & HCR_E2H) { > + /* The ASID field is active. */ > + } > +} > + > static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > @@ -4844,10 +4853,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { > .resetvalue =3D 0 }, > { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, > .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, > - .access =3D PL2_RW, > - /* no .writefn needed as this can't cause an ASID change; > - * no .raw_writefn or .resetfn needed as we never use mask/base_ma= sk > - */ > + .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, > + /* no .raw_writefn or .resetfn needed as we never use mask/base_ma= sk */ > .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, > { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, > .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, > @@ -4881,7 +4888,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { > .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, > { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, > .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, > - .access =3D PL2_RW, .resetvalue =3D 0, > + .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_= el2_write, > .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, > { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, > .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, > @@ -6807,6 +6814,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) > .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 = =3D 1, > .access =3D PL2_RW, > .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[= 2]) }, > + { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, > + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 = =3D 1, > + .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, > + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, > REGINFO_SENTINEL > }; > define_arm_cp_regs(cpu, vhe_reginfo); Otherwise: Reviewed-by: Alex Benn=C3=A9e -- Alex Benn=C3=A9e