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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <abef9b59-9f7e-8871-7d36-67c7612457ed@linaro.org>
Date: Fri, 06 Apr 2018 14:03:36 +0100
Message-ID: <876054cwrb.fsf@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH v2 05/67] target/arm: Implement SVE load
 vector/predicate
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To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org


Richard Henderson <richard.henderson@linaro.org> writes:

> On 04/03/2018 07:26 PM, Alex Benn=C3=A9e wrote:
>> You don't use it yet but probably worth a:
>>
>> static inline int ffr_full_reg_offset(DisasContext *s)
>> {
>>     return pred_full_reg_offset(s, 16);
>> }
>>
>> here when you get to it to avoid the magic 16 appearing in the main code.
>
> Hum.  Most of the places that ffr is touched is in sve.decode.
> I could certainly enhance the grammar there to allow a symbol
> there instead of a number.
>
> But I don't think treating ffr differently from a regular pr
> register, as above, is a good idea.  At best I would use
>
>   pred_full_reg_offset(s, FFR_PRED_NUM)

That would a fine alternative ;-)

--
Alex Benn=C3=A9e