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[78.55.154.8]) by smtp.gmail.com with ESMTPSA id z27-20020a50cd1b000000b004af516b5010sm2761734edi.94.2023.02.27.00.13.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Feb 2023 00:13:14 -0800 (PST) Date: Mon, 27 Feb 2023 08:13:08 +0000 From: Bernhard Beschow To: BALATON Zoltan CC: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Gerd Hoffmann , Daniel Henrique Barboza , Peter Maydell , philmd@linaro.org, Jiaxun Yang , ReneEngel80@emailn.de Subject: Re: [PATCH v3 4/8] hw/isa/vt82c686: Implement PCI IRQ routing In-Reply-To: <04111f8e-e24d-2a61-d359-f20f8cd4634e@eik.bme.hu> References: <0fd9eac9174a840054c511fbc015048929c7bc40.1677445307.git.balaton@eik.bme.hu> <04111f8e-e24d-2a61-d359-f20f8cd4634e@eik.bme.hu> Message-ID: <877517F9-2205-413F-A408-72D36B5142EB@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=shentey@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 26=2E Februar 2023 23:33:20 UTC schrieb BALATON Zoltan : >On Sun, 26 Feb 2023, Bernhard Beschow wrote: >> Am 25=2E Februar 2023 18:11:49 UTC schrieb BALATON Zoltan : >>> From: Bernhard Beschow >>>=20 >>> The real VIA south bridges implement a PCI IRQ router which is configu= red >>> by the BIOS or the OS=2E In order to respect these configurations, QEM= U >>> needs to implement it as well=2E >>>=20 >>> Note: The implementation was taken from piix4_set_irq() in hw/isa/piix= 4=2E >>>=20 >>> Signed-off-by: Bernhard Beschow >>> [balaton: declare gpio inputs instead of changing pci bus irqs so it c= an >>> be connected in board code; remove some empty lines] >>> Signed-off-by: BALATON Zoltan >>> Tested-by: Rene Engel >>> --- >>> hw/isa/vt82c686=2Ec | 39 +++++++++++++++++++++++++++++++++++++++ >>> 1 file changed, 39 insertions(+) >>>=20 >>> diff --git a/hw/isa/vt82c686=2Ec b/hw/isa/vt82c686=2Ec >>> index 3f9bd0c04d=2E=2E4025f9bcdc 100644 >>> --- a/hw/isa/vt82c686=2Ec >>> +++ b/hw/isa/vt82c686=2Ec >>> @@ -604,6 +604,44 @@ static void via_isa_request_i8259_irq(void *opaqu= e, int irq, int level) >>> qemu_set_irq(s->cpu_intr, level); >>> } >>>=20 >>> +static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num) >>> +{ >>> + switch (irq_num) { >>> + case 0: >>> + return s->dev=2Econfig[0x55] >> 4; >>> + case 1: >>> + return s->dev=2Econfig[0x56] & 0xf; >>> + case 2: >>> + return s->dev=2Econfig[0x56] >> 4; >>> + case 3: >>> + return s->dev=2Econfig[0x57] >> 4; >>> + } >>> + return 0; >>> +} >>> + >>> +static void via_isa_set_pci_irq(void *opaque, int irq_num, int level) >>> +{ >>> + ViaISAState *s =3D opaque; >>> + PCIBus *bus =3D pci_get_bus(&s->dev); >>> + int pic_irq; >>> + >>> + /* now we change the pic irq level according to the via irq mappi= ngs */ >>> + /* XXX: optimize */ >>> + pic_irq =3D via_isa_get_pci_irq(s, irq_num); >>> + if (pic_irq < ISA_NUM_IRQS) { >>> + int i, pic_level; >>> + >>> + /* The pic level is the logical OR of all the PCI irqs mapped= to it=2E */ >>> + pic_level =3D 0; >>> + for (i =3D 0; i < PCI_NUM_PINS; i++) { >>> + if (pic_irq =3D=3D via_isa_get_pci_irq(s, i)) { >>> + pic_level |=3D pci_bus_get_irq_level(bus, i); >>> + } >>> + } >>> + qemu_set_irq(s->isa_irqs[pic_irq], pic_level); >>> + } >>> +} >>> + >>> static void via_isa_realize(PCIDevice *d, Error **errp) >>> { >>> ViaISAState *s =3D VIA_ISA(d); >>> @@ -614,6 +652,7 @@ static void via_isa_realize(PCIDevice *d, Error **= errp) >>> int i; >>>=20 >>> qdev_init_gpio_out(dev, &s->cpu_intr, 1); >>> + qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM= _PINS); >>=20 >> This line is a Pegasos2 specific addition for fixing its IRQ handling= =2E Since this code must also work with the Fuloong2e board we should aim f= or a minimal changeset here which renders this line out of scope=2E >>=20 >> Let's keep the two series separate since now I need to watch two series= for comments=2E Please use Based-on: tag next time instead=2E > >Well, it's not=2E It's part of the QDev model for VT8231 that allows it t= o be connected by boards so I think this belongs here otherwise this won't = even compile because the function you've added would be unused and bail on = -Werror=2E Let's not make this more difficult than it is=2E I'm OK with rea= sonable changes but what's your goal now? You can't get rid of this line as= it's how QDev can model it=2E Either I have to call into this model or hav= e to export these pins as gpios=2E Exporting the pins is a separate aspect on top of implementing PCI IRQ rou= ting=2E To make this clear and obvious this should be a dedicated patch=2E = In case either patch has an issue this would also ease and therefore acelle= rate discussions=2E Best regards, Bernhard > >Regards, >BALATON Zoltan > >> Thanks, >> Bernhard >>=20 >>> isa_irq =3D qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); >>> isa_bus =3D isa_bus_new(dev, pci_address_space(d), pci_address_spa= ce_io(d), >>> errp); >>=20 >>=20