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Fri, 24 Jun 2022 18:48:01 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D2125AC065; Fri, 24 Jun 2022 18:48:00 +0000 (GMT) Received: from localhost (unknown [9.160.103.235]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTPS; Fri, 24 Jun 2022 18:48:00 +0000 (GMT) From: Fabiano Rosas To: Leandro Lupori , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, Leandro Lupori Subject: Re: [PATCH v2 3/3] target/ppc: Check page dir/table base alignment In-Reply-To: <20220624171653.143740-4-leandro.lupori@eldorado.org.br> References: <20220624171653.143740-1-leandro.lupori@eldorado.org.br> <20220624171653.143740-4-leandro.lupori@eldorado.org.br> Date: Fri, 24 Jun 2022 15:47:59 -0300 Message-ID: <877d55c2zk.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-GCONF: 00 X-Proofpoint-GUID: HuOqnVkbO-j_npQnbf2TSpk3bWW5Ljft X-Proofpoint-ORIG-GUID: l4wMUQNC_l8SA5MNWh65VMJg8FA1h9W3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-06-24_08,2022-06-23_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 adultscore=0 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206240072 Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Leandro Lupori writes: > Check if each page dir/table base address is properly aligned and > log a guest error if not, as real hardware behave incorrectly in > this case. I think the commit message could be clearer, something like: According to PowerISA 3.1B, Book III 6.7.6 programming note, the page directory base addresses are expected to be aligned to their size. Real hardware seems to rely on that and will access the wrong address if they are misaligned. This results in a translation failure even if the page tables seem to be properly populated. Let's make sure we capture this assumption in the code to help anyone implementing page tables. > > Signed-off-by: Leandro Lupori > --- > target/ppc/mmu-radix64.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c > index 339cf5b4d8..1e7d932893 100644 > --- a/target/ppc/mmu-radix64.c > +++ b/target/ppc/mmu-radix64.c > @@ -280,6 +280,14 @@ static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr, > *psize -= *nls; > if (!(pde & R_PTE_LEAF)) { /* Prepare for next iteration */ > *nls = pde & R_PDE_NLS; > + > + if ((pde & R_PDE_NLB) & MAKE_64BIT_MASK(0, *nls + 3)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: misaligned page dir/table base: 0x%"VADDR_PRIx > + " page dir size: 0x"TARGET_FMT_lx"\n", > + __func__, (pde & R_PDE_NLB), BIT(*nls + 3)); > + } > + > index = eaddr >> (*psize - *nls); /* Shift */ > index &= ((1UL << *nls) - 1); /* Mask */ > *pte_addr = (pde & R_PDE_NLB) + (index * sizeof(pde)); > @@ -295,6 +303,13 @@ static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr, > uint64_t index, pde, rpn, mask; > int level = 0; > > + if (base_addr & MAKE_64BIT_MASK(0, nls + 3)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: misaligned page dir base: 0x%"VADDR_PRIx > + " page dir size: 0x"TARGET_FMT_lx"\n", > + __func__, base_addr, BIT(nls + 3)); > + } > + > index = eaddr >> (*psize - nls); /* Shift */ > index &= ((1UL << nls) - 1); /* Mask */ > *pte_addr = base_addr + (index * sizeof(pde));