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Tue, 22 Jun 2021 08:48:35 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1lvc5B-0093Qj-TK; Tue, 22 Jun 2021 09:48:34 +0100 Date: Tue, 22 Jun 2021 09:48:33 +0100 Message-ID: <877dimcmji.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Subject: Re: [PATCH v17 4/6] KVM: arm64: Expose KVM_ARM_CAP_MTE In-Reply-To: References: <20210621111716.37157-1-steven.price@arm.com> <20210621111716.37157-5-steven.price@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, steven.price@arm.com, catalin.marinas@arm.com, will@kernel.org, dgilbert@redhat.com, qemu-devel@nongnu.org, Dave.Martin@arm.com, quintela@redhat.com, richard.henderson@linaro.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Received-SPF: pass client-ip=198.145.29.99; envelope-from=maz@kernel.org; helo=mail.kernel.org X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Juan Quintela , Catalin Marinas , Richard Henderson , qemu-devel@nongnu.org, "Dr. David Alan Gilbert" , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Steven Price , Will Deacon , Dave Martin , linux-kernel@vger.kernel.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 22 Jun 2021 09:07:51 +0100, Fuad Tabba wrote: > > Hi, > > On Mon, Jun 21, 2021 at 12:18 PM Steven Price wrote: > > > > It's now safe for the VMM to enable MTE in a guest, so expose the > > capability to user space. > > > > Reviewed-by: Catalin Marinas > > Signed-off-by: Steven Price > > --- > > arch/arm64/kvm/arm.c | 9 +++++++++ > > arch/arm64/kvm/reset.c | 4 ++++ > > arch/arm64/kvm/sys_regs.c | 3 +++ > > 3 files changed, 16 insertions(+) > > > > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > > index e720148232a0..28ce26a68f09 100644 > > --- a/arch/arm64/kvm/arm.c > > +++ b/arch/arm64/kvm/arm.c > > @@ -93,6 +93,12 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, > > r = 0; > > kvm->arch.return_nisv_io_abort_to_user = true; > > break; > > + case KVM_CAP_ARM_MTE: > > + if (!system_supports_mte() || kvm->created_vcpus) > > + return -EINVAL; > > + r = 0; > > + kvm->arch.mte_enabled = true; > > + break; > > default: > > r = -EINVAL; > > break; > > @@ -237,6 +243,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) > > */ > > r = 1; > > break; > > + case KVM_CAP_ARM_MTE: > > + r = system_supports_mte(); > > + break; > > case KVM_CAP_STEAL_TIME: > > r = kvm_arm_pvtime_supported(); > > break; > > diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c > > index d37ebee085cf..9e6922b9503a 100644 > > --- a/arch/arm64/kvm/reset.c > > +++ b/arch/arm64/kvm/reset.c > > @@ -244,6 +244,10 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) > > switch (vcpu->arch.target) { > > default: > > if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) { > > + if (vcpu->kvm->arch.mte_enabled) { > > + ret = -EINVAL; > > + goto out; > > + } > > pstate = VCPU_RESET_PSTATE_SVC; > > } else { > > pstate = VCPU_RESET_PSTATE_EL1; > > nit: I was wondering whether this check would be better suited in > kvm_vcpu_set_target, rather than here (kvm_reset_vcpu). kvm_reset_vcpu > is called by kvm_vcpu_set_target, but kvm_vcpu_set_target is where > checking for supported features happens. It might be better to group > all such checks together. I don't think that there is any risk of this > feature being toggled by the other call path to kvm_reset_vcpu (via > check_vcpu_requests). We already group the 32bit related compatibility checks in vcpu_allowed_register_width(), and this is where I think this should move to. I've provisionally added the change below. M. diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 9e6922b9503a..cba7872d69a8 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -176,6 +176,10 @@ static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu) if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit) return false; + /* MTE is incompatible with AArch32 */ + if (kvm_has_mte(vcpu->kvm) && is32bit) + return false; + /* Check that the vcpus are either all 32bit or all 64bit */ kvm_for_each_vcpu(i, tmp, vcpu->kvm) { if (vcpu_has_feature(tmp, KVM_ARM_VCPU_EL1_32BIT) != is32bit) @@ -244,10 +248,6 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu) switch (vcpu->arch.target) { default: if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) { - if (vcpu->kvm->arch.mte_enabled) { - ret = -EINVAL; - goto out; - } pstate = VCPU_RESET_PSTATE_SVC; } else { pstate = VCPU_RESET_PSTATE_EL1; -- Without deviation from the norm, progress is not possible.