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From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-arm@nongnu.org
Cc: "Andrew Jeffery" <andrew@aj.id.au>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Cédric Le Goater" <clg@kaod.org>,
	qemu-devel@nongnu.org
Subject: Re: [PATCH v2 2/4] aspeed/scu: Fix W1C behavior
Date: Wed, 13 Nov 2019 12:30:34 +0000	[thread overview]
Message-ID: <877e447yc5.fsf@linaro.org> (raw)
In-Reply-To: <20191113005201.19005-3-joel@jms.id.au>


Joel Stanley <joel@jms.id.au> writes:

> This models the clock write one to clear registers, and fixes up some
> incorrect behavior in all of the write to clear registers.
>
> There was also a typo in one of the register definitions.
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
>  hw/misc/aspeed_scu.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> index 717509bc5460..aac4645f8c3c 100644
> --- a/hw/misc/aspeed_scu.c
> +++ b/hw/misc/aspeed_scu.c
> @@ -98,7 +98,7 @@
>  #define AST2600_CLK_STOP_CTRL     TO_REG(0x80)
>  #define AST2600_CLK_STOP_CTRL_CLR TO_REG(0x84)
>  #define AST2600_CLK_STOP_CTRL2     TO_REG(0x90)
> -#define AST2600_CLK_STOP_CTR2L_CLR TO_REG(0x94)
> +#define AST2600_CLK_STOP_CTRL2_CLR TO_REG(0x94)
>  #define AST2600_SDRAM_HANDSHAKE   TO_REG(0x100)
>  #define AST2600_HPLL_PARAM        TO_REG(0x200)
>  #define AST2600_HPLL_EXT          TO_REG(0x204)
> @@ -532,11 +532,12 @@ static uint64_t aspeed_ast2600_scu_read(void *opaque, hwaddr offset,
>      return s->regs[reg];
>  }
>
> -static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data,
> +static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data64,
>                                       unsigned size)
>  {
>      AspeedSCUState *s = ASPEED_SCU(opaque);
>      int reg = TO_REG(offset);
> +    uint32_t data = data64;

Does it make much difference silently truncating to 32 bit here vs in
the actual set further down? AFAICT most _write functions just deal with
it at the final set.

>
>      if (reg >= ASPEED_AST2600_SCU_NR_REGS) {
>          qemu_log_mask(LOG_GUEST_ERROR,
> @@ -563,15 +564,19 @@ static void aspeed_ast2600_scu_write(void *opaque, hwaddr offset, uint64_t data,
>          /* fall through */
>      case AST2600_SYS_RST_CTRL:
>      case AST2600_SYS_RST_CTRL2:
> +    case AST2600_CLK_STOP_CTRL:
> +    case AST2600_CLK_STOP_CTRL2:
>          /* W1S (Write 1 to set) registers */
>          s->regs[reg] |= data;
>          return;
>      case AST2600_SYS_RST_CTRL_CLR:
>      case AST2600_SYS_RST_CTRL2_CLR:
> +    case AST2600_CLK_STOP_CTRL_CLR:
> +    case AST2600_CLK_STOP_CTRL2_CLR:
>      case AST2600_HW_STRAP1_CLR:
>      case AST2600_HW_STRAP2_CLR:
>          /* W1C (Write 1 to clear) registers */
> -        s->regs[reg] &= ~data;
> +        s->regs[reg - 1] &= ~data;

It might be worth expanding the W1C comment just to mention the
alignment of _CLR vs _CTRL registers.

Otherwise:

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>


>          return;
>
>      case AST2600_RNG_DATA:


--
Alex Bennée


  reply	other threads:[~2019-11-13 12:31 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-13  0:51 [PATCH v2 0/4] arm/aspeed: Watchdog and SDRAM fixes Joel Stanley
2019-11-13  0:51 ` [PATCH v2 1/4] aspeed/sdmc: Make ast2600 default 1G Joel Stanley
2019-11-13 12:21   ` Alex Bennée
2019-11-13  0:51 ` [PATCH v2 2/4] aspeed/scu: Fix W1C behavior Joel Stanley
2019-11-13 12:30   ` Alex Bennée [this message]
2019-11-13  0:52 ` [PATCH v2 3/4] watchdog/aspeed: Improve watchdog timeout message Joel Stanley
2019-11-13 12:32   ` Alex Bennée
2019-11-13  0:52 ` [PATCH v2 4/4] watchdog/aspeed: Fix AST2600 frequency behaviour Joel Stanley
2019-11-13 12:39   ` Alex Bennée

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