From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fYBI0-0000v1-Km for qemu-devel@nongnu.org; Wed, 27 Jun 2018 10:19:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fYBHx-00056L-BX for qemu-devel@nongnu.org; Wed, 27 Jun 2018 10:19:20 -0400 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]:34273) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fYBHx-000557-0h for qemu-devel@nongnu.org; Wed, 27 Jun 2018 10:19:17 -0400 Received: by mail-wm0-x22c.google.com with SMTP id l15-v6so18186113wmc.1 for ; Wed, 27 Jun 2018 07:19:16 -0700 (PDT) References: <20180621015359.12018-1-richard.henderson@linaro.org> <20180621015359.12018-6-richard.henderson@linaro.org> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <20180621015359.12018-6-richard.henderson@linaro.org> Date: Wed, 27 Jun 2018 15:19:14 +0100 Message-ID: <877emkwbvh.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v5 05/35] target/arm: Implement SVE integer convert to floating-point List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org Richard Henderson writes: > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e > --- > target/arm/helper-sve.h | 30 +++++++++++++ > target/arm/sve_helper.c | 38 ++++++++++++++++ > target/arm/translate-sve.c | 90 ++++++++++++++++++++++++++++++++++++++ > target/arm/sve.decode | 22 ++++++++++ > 4 files changed, 180 insertions(+) > > diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h > index b768128951..185112e1d2 100644 > --- a/target/arm/helper-sve.h > +++ b/target/arm/helper-sve.h > @@ -720,6 +720,36 @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG, > DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG, > void, ptr, ptr, ptr, ptr, i32) > > +DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_scvt_dh, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_scvt_ss, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_scvt_sd, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_scvt_ds, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_scvt_dd, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > + > +DEF_HELPER_FLAGS_5(sve_ucvt_hh, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_ucvt_sh, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_ucvt_dh, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_ucvt_ss, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_ucvt_sd, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_ucvt_ds, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > +DEF_HELPER_FLAGS_5(sve_ucvt_dd, TCG_CALL_NO_RWG, > + void, ptr, ptr, ptr, ptr, i32) > + > DEF_HELPER_FLAGS_4(sve_ld1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) > DEF_HELPER_FLAGS_4(sve_ld2bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) > DEF_HELPER_FLAGS_4(sve_ld3bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) > diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c > index f20774e240..a2f034820a 100644 > --- a/target/arm/sve_helper.c > +++ b/target/arm/sve_helper.c > @@ -2811,6 +2811,44 @@ uint32_t HELPER(sve_while)(void *vd, uint32_t coun= t, uint32_t pred_desc) > return predtest_ones(d, oprsz, esz_mask); > } > > +/* Fully general two-operand expander, controlled by a predicate, > + * With the extra float_status parameter. > + */ > +#define DO_ZPZ_FP(NAME, TYPE, H, OP) \ > +void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t d= esc) \ > +{ \ > + intptr_t i =3D simd_oprsz(desc); \ > + uint64_t *g =3D vg; \ > + do { \ > + uint64_t pg =3D g[(i - 1) >> 6]; \ > + do { \ > + i -=3D sizeof(TYPE); \ > + if (likely((pg >> (i & 63)) & 1)) { \ > + TYPE nn =3D *(TYPE *)(vn + H(i)); \ > + *(TYPE *)(vd + H(i)) =3D OP(nn, status); \ > + } \ > + } while (i & 63); \ > + } while (i !=3D 0); \ > +} > + > +DO_ZPZ_FP(sve_scvt_hh, uint16_t, H1_2, int16_to_float16) > +DO_ZPZ_FP(sve_scvt_sh, uint32_t, H1_4, int32_to_float16) > +DO_ZPZ_FP(sve_scvt_ss, uint32_t, H1_4, int32_to_float32) > +DO_ZPZ_FP(sve_scvt_sd, uint64_t, , int32_to_float64) > +DO_ZPZ_FP(sve_scvt_dh, uint64_t, , int64_to_float16) > +DO_ZPZ_FP(sve_scvt_ds, uint64_t, , int64_to_float32) > +DO_ZPZ_FP(sve_scvt_dd, uint64_t, , int64_to_float64) > + > +DO_ZPZ_FP(sve_ucvt_hh, uint16_t, H1_2, uint16_to_float16) > +DO_ZPZ_FP(sve_ucvt_sh, uint32_t, H1_4, uint32_to_float16) > +DO_ZPZ_FP(sve_ucvt_ss, uint32_t, H1_4, uint32_to_float32) > +DO_ZPZ_FP(sve_ucvt_sd, uint64_t, , uint32_to_float64) > +DO_ZPZ_FP(sve_ucvt_dh, uint64_t, , uint64_to_float16) > +DO_ZPZ_FP(sve_ucvt_ds, uint64_t, , uint64_to_float32) > +DO_ZPZ_FP(sve_ucvt_dd, uint64_t, , uint64_to_float64) > + > +#undef DO_ZPZ_FP > + > /* > * Load contiguous data, protected by a governing predicate. > */ > diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c > index 83de87ee0e..7639e589f5 100644 > --- a/target/arm/translate-sve.c > +++ b/target/arm/translate-sve.c > @@ -3425,6 +3425,96 @@ DO_FP3(FRSQRTS, rsqrts) > > #undef DO_FP3 > > + > +/* > + *** SVE Floating Point Unary Operations Prediated Group > + */ > + > +static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, > + bool is_fp16, gen_helper_gvec_3_ptr *fn) > +{ > + if (sve_access_check(s)) { > + unsigned vsz =3D vec_full_reg_size(s); > + TCGv_ptr status =3D get_fpstatus_ptr(is_fp16); > + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), > + vec_full_reg_offset(s, rn), > + pred_full_reg_offset(s, pg), > + status, vsz, vsz, 0, fn); > + tcg_temp_free_ptr(status); > + } > + return true; > +} > + > +static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_= hh); > +} > + > +static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_= sh); > +} > + > +static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_= dh); > +} > + > +static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt= _ss); > +} > + > +static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt= _ds); > +} > + > +static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt= _sd); > +} > + > +static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt= _dd); > +} > + > +static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_= hh); > +} > + > +static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_= sh); > +} > + > +static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_= dh); > +} > + > +static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt= _ss); > +} > + > +static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt= _ds); > +} > + > +static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt= _sd); > +} > + > +static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t ins= n) > +{ > + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt= _dd); > +} > + > /* > *** SVE Memory - 32-bit Gather and Unsized Contiguous Group > */ > diff --git a/target/arm/sve.decode b/target/arm/sve.decode > index 606c4f623c..3abdb87cf5 100644 > --- a/target/arm/sve.decode > +++ b/target/arm/sve.decode > @@ -133,6 +133,9 @@ > @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz > @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz > > +# One register operand, with governing predicate, no vector element size > +@rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz= esz=3D0 > + > # Two register operands with a 6-bit signed immediate. > @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri > > @@ -681,6 +684,25 @@ FTSMUL 01100101 .. 0 ..... 000 011 ..... ..= ... @rd_rn_rm > FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm > FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm > > +### SVE FP Unary Operations Predicated Group > + > +# SVE integer convert to floating-point > +SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_r= n_e0 > +SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_r= n_e0 > +SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_r= n_e0 > +SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_r= n_e0 > +SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_r= n_e0 > +SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_r= n_e0 > +SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_r= n_e0 > + > +UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_r= n_e0 > +UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_r= n_e0 > +UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_r= n_e0 > +UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_r= n_e0 > +UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_r= n_e0 > +UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_r= n_e0 > +UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_r= n_e0 > + > ### SVE Memory - 32-bit Gather and Unsized Contiguous Group > > # SVE load predicate register -- Alex Benn=C3=A9e