From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aMEjX-0004th-W8 for qemu-devel@nongnu.org; Thu, 21 Jan 2016 07:53:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aMEjS-0004VQ-9H for qemu-devel@nongnu.org; Thu, 21 Jan 2016 07:53:03 -0500 Received: from mail-wm0-x22c.google.com ([2a00:1450:400c:c09::22c]:37328) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aMEjR-0004Ut-Tk for qemu-devel@nongnu.org; Thu, 21 Jan 2016 07:52:58 -0500 Received: by mail-wm0-x22c.google.com with SMTP id n5so79136169wmn.0 for ; Thu, 21 Jan 2016 04:52:57 -0800 (PST) References: <1453297780-12514-1-git-send-email-edgar.iglesias@gmail.com> <1453297780-12514-4-git-send-email-edgar.iglesias@gmail.com> <20160120172355.GW29396@toto> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <20160120172355.GW29396@toto> Date: Thu, 21 Jan 2016 12:52:54 +0000 Message-ID: <877fj3ccwp.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v1 3/3] target-arm: Implement the S2 MMU inputsize < pamax check List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Edgar E. Iglesias writes: > On Wed, Jan 20, 2016 at 02:49:40PM +0100, Edgar E. Iglesias wrote: >> From: "Edgar E. Iglesias" >> >> Implement the inputsize < pamax check for Stage 2 translations. >> We have multiple choices for how to respond to errors and >> choose to fault. >> >> Signed-off-by: Edgar E. Iglesias >> --- >> target-arm/helper.c | 15 +++++++++++---- >> 1 file changed, 11 insertions(+), 4 deletions(-) >> >> diff --git a/target-arm/helper.c b/target-arm/helper.c >> index 4abeb4d..e1fa209 100644 >> --- a/target-arm/helper.c >> +++ b/target-arm/helper.c >> @@ -6808,7 +6808,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, >> */ >> int startlevel = extract32(tcr->raw_tcr, 6, 2); >> unsigned int pamax = arm_pamax(cpu); >> - bool ok; >> + bool ok = true; >> >> if (va_size == 32 || stride == 9) { >> /* AArch32 or 4KB pages */ >> @@ -6818,9 +6818,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, >> level = 3 - startlevel; >> } >> >> - /* Check that the starting level is valid. */ >> - ok = check_s2_startlevel(cpu, va_size == 64, level, >> - inputsize, stride, pamax); >> + if (inputsize > pamax && >> + (arm_el_is_aa64(env, 1) || inputsize > 40)) { > > I realized that this check should only be done for AArch64... > Will fix that for v2. > > Something like the following: > > if (arm_el_is_aa64(env, el) && > inputsize > pamax && > (arm_el_is_aa64(env, 1) || inputsize > 40)) { > /* We have multiple choices but choose to fault. */ > ok = false; > } > OK, I'll await the next revision. > > Cheers, > Edgar > > >> + /* We have multiple choices but choose to fault. */ >> + ok = false; >> + } >> + if (ok) { >> + /* Check that the starting level is valid. */ >> + ok = check_s2_startlevel(cpu, va_size == 64, level, >> + inputsize, stride, pamax); >> + } >> if (!ok) { >> /* AArch64 reports these as level 0 faults. >> * AArch32 reports these as level 1 faults. >> -- >> 1.9.1 >> -- Alex Bennée