From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aGrdy-0001XB-1f for qemu-devel@nongnu.org; Wed, 06 Jan 2016 12:13:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aGrdu-0005x7-R4 for qemu-devel@nongnu.org; Wed, 06 Jan 2016 12:13:05 -0500 Received: from mail-wm0-x236.google.com ([2a00:1450:400c:c09::236]:36025) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aGrdu-0005wu-LP for qemu-devel@nongnu.org; Wed, 06 Jan 2016 12:13:02 -0500 Received: by mail-wm0-x236.google.com with SMTP id l65so66944629wmf.1 for ; Wed, 06 Jan 2016 09:13:02 -0800 (PST) References: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> <1450082498-27109-9-git-send-email-a.rigo@virtualopensystems.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1450082498-27109-9-git-send-email-a.rigo@virtualopensystems.com> Date: Wed, 06 Jan 2016 17:13:00 +0000 Message-ID: <877fjmd42r.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [RFC v6 08/14] target-arm: Add atomic_clear helper for CLREX insn List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alvise Rigo Cc: mttcg@listserver.greensocs.com, claudio.fontana@huawei.com, qemu-devel@nongnu.org, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, rth@twiddle.net Alvise Rigo writes: > Add a simple helper function to emulate the CLREX instruction. And now I see ;-) I suspect this should be merged with the other helpers as a generic helper. > > Suggested-by: Jani Kokkonen > Suggested-by: Claudio Fontana > Signed-off-by: Alvise Rigo > --- > target-arm/helper.h | 2 ++ > target-arm/op_helper.c | 6 ++++++ > target-arm/translate.c | 1 + > 3 files changed, 9 insertions(+) > > diff --git a/target-arm/helper.h b/target-arm/helper.h > index c2a85c7..37cec49 100644 > --- a/target-arm/helper.h > +++ b/target-arm/helper.h > @@ -532,6 +532,8 @@ DEF_HELPER_2(dc_zva, void, env, i64) > DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) > DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) > > +DEF_HELPER_1(atomic_clear, void, env) > + > #ifdef TARGET_AARCH64 > #include "helper-a64.h" > #endif > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 6cd54c8..5a67557 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -50,6 +50,12 @@ static int exception_target_el(CPUARMState *env) > return target_el; > } > > +void HELPER(atomic_clear)(CPUARMState *env) > +{ > + ENV_GET_CPU(env)->excl_protected_range.begin = -1; Is there not a defined reset value EXCLUSIVE_RESET_ADDR we should use here? > + ENV_GET_CPU(env)->ll_sc_context = false; > +} > + > uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, > uint32_t rn, uint32_t maxindex) > { > diff --git a/target-arm/translate.c b/target-arm/translate.c > index e88d8a3..e0362e0 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7514,6 +7514,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, > static void gen_clrex(DisasContext *s) > { > #ifdef CONFIG_TCG_USE_LDST_EXCL > + gen_helper_atomic_clear(cpu_env); > #else > tcg_gen_movi_i64(cpu_exclusive_addr, -1); > #endif -- Alex Bennée