From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46419) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V4fj4-0001Ag-6y for qemu-devel@nongnu.org; Wed, 31 Jul 2013 19:22:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V4fiy-0000kf-1J for qemu-devel@nongnu.org; Wed, 31 Jul 2013 19:22:38 -0400 Received: from mail-oa0-f42.google.com ([209.85.219.42]:56537) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V4fix-0000kX-SF for qemu-devel@nongnu.org; Wed, 31 Jul 2013 19:22:31 -0400 Received: by mail-oa0-f42.google.com with SMTP id i18so2929587oag.29 for ; Wed, 31 Jul 2013 16:22:31 -0700 (PDT) From: Anthony Liguori In-Reply-To: <51F99632.8000209@ozlabs.ru> References: <1373614704-15581-1-git-send-email-aik@ozlabs.ru> <87zjt2a9pr.fsf@codemonkey.ws> <51F99632.8000209@ozlabs.ru> Date: Wed, 31 Jul 2013 18:22:29 -0500 Message-ID: <877gg61fii.fsf@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Re: [Qemu-devel] [PATCH] spapr-pci: rework MSI/MSIX List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy Cc: David Gibson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Alexander Graf Alexey Kardashevskiy writes: > On 08/01/2013 04:02 AM, Anthony Liguori wrote: >> Alexey Kardashevskiy writes: >> >>> On the sPAPR platform a guest allocates MSI/MSIX vectors via RTAS >>> hypercalls which return global IRQ numbers to a guest so it only >>> operates with those and never touches MSIMessage. >>> >>> Therefore MSIMessage handling is completely hidden in QEMU. >>> >>> Previously every sPAPR PCI host bridge implemented its own MSI window >>> to catch msi_notify()/msix_notify() calls from QEMU devices (virtio-pci >>> or vfio) and route them to the guest via qemu_pulse_irq(). >>> MSIMessage used to be encoded as: >>> .addr - address within the PHB MSI window; >>> .data - the device index on PHB plus vector number. >>> The MSI MR write function translated this MSIMessage to a global IRQ >>> number and called qemu_pulse_irq(). >>> >>> However the total number of IRQs is not really big (at the moment it is >>> 1024 IRQs starting from 4096) and even 16bit data field of MSIMessage >>> seems to be enough to store an IRQ number there. >>> >>> This simplifies MSI handling in sPAPR PHB. Specifically, this does: >>> 1. remove a MSI window from a PHB; >>> 2. add a single memory region for all MSIs to sPAPREnvironment >>> and spapr_pci_msi_init() to initialize it; >>> 3. encode MSIMessage as: >>> * .addr - a fixed address of SPAPR_PCI_MSI_WINDOW==0x40000000000ULL; >>> * .data as an IRQ number. >>> 4. change IRQ allocator to align first IRQ number in a block for MSI. >>> MSI uses lower bits to specify the vector number so the first IRQ has to >>> be aligned. MSIX does not need any special allocator though. >>> >>> Signed-off-by: Alexey Kardashevskiy >> >> Reviewed-by: Anthony Liguori >> >> Does this actually fix any bug or is this just refactoring? If it's the >> later, it'll have to wait until after the 1.7 window opens up. > > > This is refactoring which should make IRQFD enablement on spapr > easier. Okay, I'll apply it after hard freeze then. Regards, Anthony Liguori > > > > -- > Alexey