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Wed, 5 Jan 2022 18:40:33 +0000 (GMT) References: <00a79b65-288f-f17c-abe4-fcfd3f7971fd@oth-regensburg.de> <85d02ac883c7cf40fbd54e8747783937e0370eaa.1641309725.git.konrad.schwarz@siemens.com> <18d1fbb3-ddff-6d3c-55a1-cbec27ac9f1e@linaro.org> <9511f23e9cdf42609866bc597f87b97e@siemens.com> User-agent: mu4e 1.7.5; emacs 28.0.90 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: "Schwarz, Konrad" Subject: Re: [PATCH v2 1/5] RISC-V: larger and more consistent register set for 'info registers' Date: Wed, 05 Jan 2022 18:21:40 +0000 In-reply-to: <9511f23e9cdf42609866bc597f87b97e@siemens.com> Message-ID: <878rvujaam.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::536 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Richard Henderson , Ralf Ramsauer , qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" "Schwarz, Konrad" writes: >> -----Original Message----- >> From: Richard Henderson >> Sent: Tuesday, January 4, 2022 21:57 >> Subject: Re: [PATCH v2 1/5] RISC-V: larger and more consistent register = set for 'info registers' >>=20 >> On 1/4/22 7:51 AM, Konrad Schwarz wrote: >> > static const int dump_csrs[] =3D { >> > + >> > +# if 0 >> > + CSR_USTATUS, >> > + CSR_UIE, >> > + CSR_UTVEC, >>=20 >> Adding huge sections of #if 0 code is not acceptable. > > I'm not sure on how to solve the dilemma of > > * transgressing on QEMUs coding guidelines on the one side > (large sections of commented out code) > > * having `info registers' output a huge swath of CSRs, > swamping the user and making the command impractical > > I feel that providing some control at compile > time via `# if' conditional compilation is preferrable to just dumping > everything. I could of course only list the CSRs that > are interesting to me, currently, but I thought it > would be better to list (almost) all of them and give at least > programmers an easy way to enable the blocks of CSRs > that are of interest to them. > > Obviously, the best solution would be to extend the command to > add a filter argument, similar to GDB's `info registers' > (i.e. info registers XXX), but I don't know how to do that in QEMU and > it would work differently from other target architectures. This is a problem that needs solving not only for "info registers" but also things like "-d cpu", gdbserver and (eventually) TCG plugins. My (so far unrealised) vision is to have a architecture independent sub-system that we can register (sic) registers. The frontends would replace their existing qemu_log and gdbserver hooks with a group aware registering function to the sub-system. For example: register_reg("x0", REG_CORE, get_gen_reg, set_gen_reg, offsetof(CPUARMSta= te, xregs[0])) register_reg(ri->name, REG_SYSTEM, get_cpreg, set_cpreg, ri); and so on. This would then provide a common point for the register value consumers to request values and sets. So we could have options like: (hmp) info registers fpu -d cpu:pc qemu_plugin_get_regset("x0-x7"); and avoid having too much per-architecture special casing. I'd also like to get rid of custom gdb XML generation in the frontends (e.g. arm_gen_dynamic_svereg_xml) and make that common functionality. > What would you suggest? --=20 Alex Benn=C3=A9e