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X-Received-From: 2a00:1450:4864:20::343 Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH v5 02/17] target/arm: Split out rebuild_hflags_a64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > On 9/5/19 11:28 AM, Alex Benn=C3=A9e wrote: >>> - >>> - if (cpu_isar_feature(aa64_bti, cpu)) { >>> - /* Note that SCTLR_EL[23].BT =3D=3D SCTLR_BT1. */ >>> - if (sctlr & (current_el =3D=3D 0 ? SCTLR_BT0 : SCTLR_BT1))= { >>> - flags =3D FIELD_DP32(flags, TBFLAG_A64, BT, 1); >>> - } >>> + flags =3D rebuild_hflags_a64(env, current_el, fp_el, mmu_idx); >>> + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { >>> flags =3D FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); >> >> It seems off to only hoist part of the BTI flag check into the helper, >> was it just missed or is there a reason? If so it could probably do with >> an additional comment. > > The part of the bti stuff that is hoisted is solely based on system regis= ters. > The BTYPE field is in PSTATE and is a very different kind of animal -- in > particular, it is not set by MSR. > > But also, comments in cpu.h say which fields are (not) cached in hflags, = and > BTYPE is so documented. > > Is your proposed comment really helpful here going forward, or do you just > think it's weird reviewing this patch, since not all BTI is treated the s= ame > after the patch? It was just weird seeing the isar_feature test twice. A mention in the commit "not all bti related flags will be cached so we have to test the feature twice" or something like that will suffice. > > > r~ -- Alex Benn=C3=A9e