From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 17/17] tests/tcg/aarch64: Add mte smoke tests
Date: Mon, 14 Jan 2019 14:22:51 +0000 [thread overview]
Message-ID: <878sznpbd0.fsf@linaro.org> (raw)
In-Reply-To: <20190114011122.5995-18-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> ??? Requires a quite recent aarch64 assembler. Use .inst instead?
How recent? Given buster is nearing release we could start using it as a
basis for the ARM cross compiler images. That is shipping gcc 8.2.0 as
of now.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tests/tcg/aarch64/mte-1.c | 27 +++++++++++++++++++++
> tests/tcg/aarch64/mte-2.c | 39 +++++++++++++++++++++++++++++++
> tests/tcg/aarch64/Makefile.target | 4 ++++
> 3 files changed, 70 insertions(+)
> create mode 100644 tests/tcg/aarch64/mte-1.c
> create mode 100644 tests/tcg/aarch64/mte-2.c
>
> diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c
> new file mode 100644
> index 0000000000..740bf506f1
> --- /dev/null
> +++ b/tests/tcg/aarch64/mte-1.c
> @@ -0,0 +1,27 @@
> +/*
> + * Memory tagging, basic pass cases.
> + */
> +
> +#include <assert.h>
> +
> +asm(".arch armv8.5-a+memtag");
> +
> +int data[16 / sizeof(int)] __attribute__((aligned(16)));
> +
> +int main(int ac, char **av)
> +{
> + int *p0 = data;
> + int *p1, *p2;
> + long c;
> +
> + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1));
> + assert(p1 != p0);
> + asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1));
> + assert(c == 0);
> +
> + asm("stg [%0]" : : "r"(p1));
> + asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0));
> + assert(p1 == p2);
> +
> + return 0;
> +}
> diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c
> new file mode 100644
> index 0000000000..4d2004ab41
> --- /dev/null
> +++ b/tests/tcg/aarch64/mte-2.c
> @@ -0,0 +1,39 @@
> +/*
> + * Memory tagging, basic fail cases.
> + */
> +
> +#include <assert.h>
> +#include <signal.h>
> +#include <stdlib.h>
> +
> +asm(".arch armv8.5-a+memtag");
> +
> +int data[16 / sizeof(int)] __attribute__((aligned(16)));
> +
> +void pass(int sig)
> +{
> + exit(0);
> +}
> +
> +int main(int ac, char **av)
> +{
> + int *p0 = data;
> + int *p1, *p2;
> + long excl = 1;
> +
> + /* Create two differently tagged pointers. */
> + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl));
> + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1));
> + assert(excl != 1);
> + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl));
> + assert(p1 != p2);
> +
> + /* Store the tag from the first pointer. */
> + asm("stg [%0]" : : "r"(p1));
> +
> + *p1 = 0;
> + signal(SIGSEGV, pass);
> + *p2 = 0;
> +
> + assert(0);
> +}
> diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
> index 3d56e7c6ea..1c4ebe894c 100644
> --- a/tests/tcg/aarch64/Makefile.target
> +++ b/tests/tcg/aarch64/Makefile.target
> @@ -19,4 +19,8 @@ AARCH64_TESTS += bti-1
> bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib
> run-bti-1: QEMU += -cpu max,guarded_pages=on
>
> +AARCH64_TESTS += mte-1 mte-2
> +mte-%: CFLAGS += -O -g
> +run-mte-%: QEMU += -cpu max
> +
> TESTS:=$(AARCH64_TESTS)
--
Alex Bennée
next prev parent reply other threads:[~2019-01-14 14:23 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-14 1:11 [Qemu-devel] [PATCH 00/17] target/arm: Implement ARMv8.5-MemTag Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 01/17] target/arm: Add MTE_ACTIVE to tb_flags Richard Henderson
2019-02-05 19:06 ` Peter Maydell
2019-02-10 0:06 ` Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 02/17] target/arm: Extract TCMA with ARMVAParameters Richard Henderson
2019-02-05 19:08 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 03/17] target/arm: Add MTE system registers Richard Henderson
2019-02-05 19:27 ` Peter Maydell
2019-02-10 1:20 ` Richard Henderson
2019-02-10 1:23 ` Richard Henderson
2019-02-10 21:40 ` Peter Maydell
2019-02-10 22:47 ` Richard Henderson
2019-02-11 9:43 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 04/17] target/arm: Fill in helper_mte_check Richard Henderson
2019-02-07 15:57 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 05/17] target/arm: Suppress tag check for sp+offset Richard Henderson
2019-02-07 16:17 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 06/17] target/arm: Implement the IRG instruction Richard Henderson
2019-02-07 16:47 ` Peter Maydell
2019-02-10 3:43 ` Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 07/17] target/arm: Implement ADDG, SUBG instructions Richard Henderson
2019-02-07 17:28 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 08/17] target/arm: Implement the GMI instruction Richard Henderson
2019-02-07 17:32 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 09/17] target/arm: Implement the SUBP instruction Richard Henderson
2019-02-07 17:38 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 10/17] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2019-02-07 17:41 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 11/17] target/arm: Implement the STGP instruction Richard Henderson
2019-02-07 17:41 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 12/17] target/arm: Implement the LDGV and STGV instructions Richard Henderson
2019-02-07 17:43 ` Peter Maydell
2019-01-14 1:11 ` [Qemu-devel] [PATCH 13/17] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2019-02-07 17:44 ` Peter Maydell
2019-02-08 17:16 ` Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 14/17] tcg: Introduce target-specific page data for user-only Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 15/17] target/arm: Add allocation tag storage " Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 16/17] target/arm: Enable MTE Richard Henderson
2019-01-14 1:11 ` [Qemu-devel] [PATCH 17/17] tests/tcg/aarch64: Add mte smoke tests Richard Henderson
2019-01-14 14:22 ` Alex Bennée [this message]
2019-01-14 21:07 ` Richard Henderson
2019-02-05 19:42 ` [Qemu-devel] [PATCH 00/17] target/arm: Implement ARMv8.5-MemTag Peter Maydell
2019-02-07 17:53 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=878sznpbd0.fsf@linaro.org \
--to=alex.bennee@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).