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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <20180501180455.11214-3-richard.henderson@linaro.org>
Date: Wed, 02 May 2018 10:47:17 +0100
Message-ID: <878t929yoq.fsf@linaro.org>
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Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 2/2] target/arm: Tidy condition
 in disas_simd_two_reg_misc
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To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, qemu-arm@nongnu.org


Richard Henderson <richard.henderson@linaro.org> writes:

> Path analysis shows that size =3D=3D 3 && !is_q has been eliminated.
>
> Fixes: Coverity CID1385853
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>

> ---
>  target/arm/translate-a64.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 97950dce1a..6d49f30b4a 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -11473,7 +11473,11 @@ static void disas_simd_two_reg_misc(DisasContext=
 *s, uint32_t insn)
>          /* All 64-bit element operations can be shared with scalar 2misc=
 */
>          int pass;
>
> -        for (pass =3D 0; pass < (is_q ? 2 : 1); pass++) {
> +        /* Coverity claims (size =3D=3D 3 && !is_q) has been eliminated
> +         * from all paths leading to here.
> +         */
> +        tcg_debug_assert(is_q);
> +        for (pass =3D 0; pass < 2; pass++) {
>              TCGv_i64 tcg_op =3D tcg_temp_new_i64();
>              TCGv_i64 tcg_res =3D tcg_temp_new_i64();


--
Alex Benn=C3=A9e