Re: [PATCH 4/5] target/arm: Support more GM blocksizes

[Richard Henderson <richard.henderson@linaro.org>]

On 8/10/23 07:23, Peter Maydell wrote:
>> +    case 4:
>> +        /* 64 bytes -> 4 tags -> 16 result bits */
>> +        ret = cpu_to_le16(*(uint16_t *)tag_mem);
> 
> Does this really make a difference compared to ldw_le_p() ?

ldw_le_p uses memcpy, though only mips and sparc hosts do not have unaligned reads, so 
perhaps it doesn't make much difference.

I had originally been thinking about atomicity, but then noticed that the pseudocode uses 
a loop and so the instruction is therefore non-atomic.


> Is it worth having an assert in CPU realize for an invalid
> blocksize, so that we can catch duff ID register values
> without having to rely on there being a test run that
> uses ldgm/stgm ?

Yes, that's a good idea.


r~