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([2602:47:d483:7301:9e4d:b830:d4fd:9164]) by smtp.gmail.com with ESMTPSA id z6-20020a170903018600b001bbdf32f011sm2122436plg.269.2023.08.10.12.10.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Aug 2023 12:10:59 -0700 (PDT) Message-ID: <8793650b-4e48-c4c1-be75-1f79692496d7@linaro.org> Date: Thu, 10 Aug 2023 12:10:57 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 4/5] target/arm: Support more GM blocksizes Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org References: <20230810023548.412310-1-richard.henderson@linaro.org> <20230810023548.412310-5-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.156, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/10/23 07:23, Peter Maydell wrote: >> + case 4: >> + /* 64 bytes -> 4 tags -> 16 result bits */ >> + ret = cpu_to_le16(*(uint16_t *)tag_mem); > > Does this really make a difference compared to ldw_le_p() ? ldw_le_p uses memcpy, though only mips and sparc hosts do not have unaligned reads, so perhaps it doesn't make much difference. I had originally been thinking about atomicity, but then noticed that the pseudocode uses a loop and so the instruction is therefore non-atomic. > Is it worth having an assert in CPU realize for an invalid > blocksize, so that we can catch duff ID register values > without having to rely on there being a test run that > uses ldgm/stgm ? Yes, that's a good idea. r~