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Mon, 01 Apr 2024 23:31:09 +0200 From: Sven Schnelle To: Richard Henderson Cc: qemu-devel@nongnu.org, Helge Deller Subject: Re: [PATCH] target/hppa: mask upper iaoq bits when returning to narrow mode In-Reply-To: (Richard Henderson's message of "Mon, 1 Apr 2024 11:21:02 -1000") References: <20240401145201.2175873-1-svens@stackframe.org> <0f5697e6-da79-424b-866d-40d11b4db0bb@linaro.org> <87msqczujz.fsf@t14.stackframe.org> Date: Mon, 01 Apr 2024 23:31:08 +0200 Message-ID: <87a5mczs6b.fsf@t14.stackframe.org> MIME-Version: 1.0 Content-Type: text/plain Received-SPF: pass client-ip=23.83.215.33; envelope-from=svens@stackframe.org; helo=chameleon.oak.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Richard Henderson writes: > On 4/1/24 10:39, Sven Schnelle wrote: >> Richard Henderson writes: >>>> For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed >>>> computation of the new IAOQ value in the signal handler. In the >>>> current code these bits are not masked when returning to narrow >>>> mode, causing java to crash. >>>> Signed-off-by: Sven Schnelle >> INT 3530: instruction tlb miss fault @ 0000000000000000:ffffffffc0000007 for 0000000000000000:40000000c0000004 >> INT 3531: external interrupt @ 0000000000000000:ffffffffc0000007 for 0000000000000000:40000000c0000004 >> INT 3532: instruction tlb miss fault @ 0000000000000000:ffffffffc0000007 for 0000000000000000:40000000c0000004 >> INT 3533: external interrupt @ 0000000000000000:ffffffffc0000007 for 0000000000000000:40000000c0000004 >> So the PSW indicates narrow mode, but IAOQ seems to contain all the >> ffff... bits. > > I believe that the IAOQ *should* contain all of the bits. The bits > should only be discarded when we form the GVA -- exactly like "ldb > 0(r2)", where r2 contains all of the offset bits. In particular, I > believe that "b,l .+8,r2" should copy all of those bits to r2 from > IAOQ_Back+4 and the fact that mainline crops those bits is a bug. > > >> Also interesting is that the second TLB miss (INT 3530) >> misses the Space ID. > > That is a bit curious, yes. > >> Any thoughts? Otherwise i need to investigate and make a wrong patch >> again :-) >> The only patch i have on top which touches target/hppa is the space >> id >> hashing mask patch: > > Ok. I do have an hppa 11.11 iso -- for clarity, what is your command-line? I'm using: ./build/qemu-system-hppa -M C3700 -m 1024 -cdrom /home/svens/parisc/hpux/11.11/HP-UX 11.11 (2004-12) - TCOE - Core OS, Install and Recovery - DVD.iso -bios /home/svens/seabios-hppa/out-64/hppa-firmware64.img -nographic -hda /home/svens/parisc/hpux1111.img -boot d The qemu i'm using is: https://github.com/svenschnelle/qemu/tree/devel You also need a special seabios-hppa version, because a special console driver is needed: https://github.com/hdeller/seabios-hppa/tree/devel