From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
Anders Roxell <anders.roxell@linaro.org>,
Evgeny Iakovlev <eiakovlev@linux.microsoft.com>
Subject: Re: [RFC PATCH] target/arm: add RAZ/WI handling for DBGDTR[TX|RX]
Date: Thu, 18 May 2023 12:09:47 +0100 [thread overview]
Message-ID: <87a5y1nbbv.fsf@linaro.org> (raw)
In-Reply-To: <CAFEAcA8fu-+YUeuhVw8mpgYXO=ueXrCecC-LkhFwoubUkMvg4Q@mail.gmail.com>
Peter Maydell <peter.maydell@linaro.org> writes:
> On Tue, 16 May 2023 at 11:44, Alex Bennée <alex.bennee@linaro.org> wrote:
>>
>> The commit b3aa2f2128 (target/arm: provide stubs for more external
>> debug registers) was added to handle HyperV's unconditional usage of
>> Debug Communications Channel. It turns out that Linux will similarly
>> break if you enable CONFIG_HVC_DCC "ARM JTAG DCC console".
>>
>> Extend the registers we RAZ/WI set to avoid this.
>
> Applied to target-arm.next, thanks.
>
> (In theory we could implement the DCC and wire it up to a
> chardev, which might be a cute way of getting early debug.)
I wondered about that - does DCC give you anything that you can't get
with semihosting (which I think also can support earlycon)?
I found it a little unclear if this is an always available feature.
Should you expect any modern Cortex/Arm chip to support DCC when
attached to jtag?
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
next prev parent reply other threads:[~2023-05-18 11:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-16 10:44 [RFC PATCH] target/arm: add RAZ/WI handling for DBGDTR[TX|RX] Alex Bennée
2023-05-16 20:15 ` Richard Henderson
2023-05-18 10:10 ` Peter Maydell
2023-05-18 11:09 ` Alex Bennée [this message]
2023-05-18 11:43 ` Peter Maydell
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