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Thu, 28 Jan 2021 11:05:46 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c18sm12975714wmk.0.2021.01.28.11.05.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Jan 2021 11:05:44 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 706BF1FF7E; Thu, 28 Jan 2021 19:05:43 +0000 (GMT) References: <20210128092814.8676-1-cfontana@suse.de> <20210128092814.8676-5-cfontana@suse.de> User-agent: mu4e 1.5.7; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Claudio Fontana Subject: Re: [PATCH v14 04/22] cpu: Move synchronize_from_tb() to tcg_ops Date: Thu, 28 Jan 2021 18:58:03 +0000 In-reply-to: <20210128092814.8676-5-cfontana@suse.de> Message-ID: <87a6ssubjs.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Thomas Huth , Eduardo Habkost , Richard Henderson , qemu-devel@nongnu.org, Roman Bolshakov , Alistair Francis , Paolo Bonzini , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Claudio Fontana writes: > From: Eduardo Habkost > > Signed-off-by: Eduardo Habkost > > [claudio: wrapped in CONFIG_TCG] > Signed-off-by: Claudio Fontana > --- > include/hw/core/cpu.h | 20 +++++++++++--------- > accel/tcg/cpu-exec.c | 4 ++-- > target/arm/cpu.c | 4 +++- > target/avr/cpu.c | 2 +- > target/hppa/cpu.c | 2 +- > target/i386/tcg/tcg-cpu.c | 2 +- > target/microblaze/cpu.c | 2 +- > target/mips/cpu.c | 4 +++- > target/riscv/cpu.c | 2 +- > target/rx/cpu.c | 2 +- > target/sh4/cpu.c | 2 +- > target/sparc/cpu.c | 2 +- > target/tricore/cpu.c | 2 +- > 13 files changed, 28 insertions(+), 22 deletions(-) > > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 96fdca39d2..b3c1bb77eb 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -87,6 +87,17 @@ typedef struct TcgCpuOperations { > * Called when the first CPU is realized. > */ > void (*initialize)(void); > + /** > + * @synchronize_from_tb: Synchronize state from a TCG #TranslationBl= ock > + * > + * This is called when we abandon execution of a TB before > + * starting it, and must set all parts of the CPU state which > + * the previous TB in the chain may not have updated. This > + * will need to do more. If this hook is not implemented then > + * the default is to call @set_pc(tb->pc). > + */ Possibly re-word a little more? ...TB in the chain may not have updated. By default when no hook is defined a call is made to @set_pc(tb->pc). If more state needs to be restored the front-end must provide a hook function and restore all the state there. > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index fa4d4ba4eb..140cb33f07 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -54,6 +54,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) > } > } >=20=20 > +#ifdef CONFIG_TCG > static void arm_cpu_synchronize_from_tb(CPUState *cs, > const TranslationBlock *tb) > { > @@ -70,6 +71,7 @@ static void arm_cpu_synchronize_from_tb(CPUState *cs, > env->regs[15] =3D tb->pc; > } > } > +#endif /* CONFIG_TCG */ Looking at the function here I wonder if we should be worried about the thumb state? Peter? static void arm_cpu_set_pc(CPUState *cs, vaddr value) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; if (is_a64(env)) { env->pc =3D value; env->thumb =3D 0; } else { env->regs[15] =3D value & ~1; env->thumb =3D value & 1; } } #ifdef CONFIG_TCG void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; /* * It's OK to look at env for the current mode here, because it's * never possible for an AArch64 TB to chain to an AArch32 TB. */ if (is_a64(env)) { env->pc =3D tb->pc; } else { env->regs[15] =3D tb->pc; } } #endif /* CONFIG_TCG */ Otherwise: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e