From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH v2 26/36] tcg: Add load_dest parameter to GVecGen2
Date: Thu, 23 Apr 2020 10:37:13 +0100 [thread overview]
Message-ID: <87a732bl12.fsf@linaro.org> (raw)
In-Reply-To: <20200422011722.13287-27-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> We have this same parameter for GVecGen2i, GVecGen3,
> and GVecGen3i. This will make some SVE2 insns easier
> to parameterize.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> include/tcg/tcg-op-gvec.h | 2 ++
> tcg/tcg-op-gvec.c | 45 ++++++++++++++++++++++++++++-----------
> 2 files changed, 34 insertions(+), 13 deletions(-)
>
> diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
> index d89f91f40e..cea6497341 100644
> --- a/include/tcg/tcg-op-gvec.h
> +++ b/include/tcg/tcg-op-gvec.h
> @@ -109,6 +109,8 @@ typedef struct {
> uint8_t vece;
> /* Prefer i64 to v64. */
> bool prefer_i64;
> + /* Load dest as a 2nd source operand. */
> + bool load_dest;
> } GVecGen2;
>
> typedef struct {
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> index 43cac1a0bf..049a55e700 100644
> --- a/tcg/tcg-op-gvec.c
> +++ b/tcg/tcg-op-gvec.c
> @@ -663,17 +663,22 @@ static void expand_clr(uint32_t dofs, uint32_t maxsz)
>
> /* Expand OPSZ bytes worth of two-operand operations using i32 elements. */
> static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
> - void (*fni)(TCGv_i32, TCGv_i32))
> + bool load_dest, void (*fni)(TCGv_i32, TCGv_i32))
> {
> TCGv_i32 t0 = tcg_temp_new_i32();
> + TCGv_i32 t1 = tcg_temp_new_i32();
> uint32_t i;
>
> for (i = 0; i < oprsz; i += 4) {
> tcg_gen_ld_i32(t0, cpu_env, aofs + i);
> - fni(t0, t0);
> - tcg_gen_st_i32(t0, cpu_env, dofs + i);
> + if (load_dest) {
> + tcg_gen_ld_i32(t1, cpu_env, dofs + i);
> + }
> + fni(t1, t0);
> + tcg_gen_st_i32(t1, cpu_env, dofs + i);
> }
> tcg_temp_free_i32(t0);
> + tcg_temp_free_i32(t1);
> }
>
> static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
> @@ -793,17 +798,22 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
>
> /* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
> static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
> - void (*fni)(TCGv_i64, TCGv_i64))
> + bool load_dest, void (*fni)(TCGv_i64, TCGv_i64))
> {
> TCGv_i64 t0 = tcg_temp_new_i64();
> + TCGv_i64 t1 = tcg_temp_new_i64();
> uint32_t i;
>
> for (i = 0; i < oprsz; i += 8) {
> tcg_gen_ld_i64(t0, cpu_env, aofs + i);
> - fni(t0, t0);
> - tcg_gen_st_i64(t0, cpu_env, dofs + i);
> + if (load_dest) {
> + tcg_gen_ld_i64(t1, cpu_env, dofs + i);
> + }
> + fni(t1, t0);
> + tcg_gen_st_i64(t1, cpu_env, dofs + i);
> }
> tcg_temp_free_i64(t0);
> + tcg_temp_free_i64(t1);
> }
>
> static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
> @@ -924,17 +934,23 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
> /* Expand OPSZ bytes worth of two-operand operations using host vectors. */
> static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
> uint32_t oprsz, uint32_t tysz, TCGType type,
> + bool load_dest,
> void (*fni)(unsigned, TCGv_vec, TCGv_vec))
> {
> TCGv_vec t0 = tcg_temp_new_vec(type);
> + TCGv_vec t1 = tcg_temp_new_vec(type);
> uint32_t i;
>
> for (i = 0; i < oprsz; i += tysz) {
> tcg_gen_ld_vec(t0, cpu_env, aofs + i);
> - fni(vece, t0, t0);
> - tcg_gen_st_vec(t0, cpu_env, dofs + i);
> + if (load_dest) {
> + tcg_gen_ld_vec(t1, cpu_env, dofs + i);
> + }
> + fni(vece, t1, t0);
> + tcg_gen_st_vec(t1, cpu_env, dofs + i);
> }
> tcg_temp_free_vec(t0);
> + tcg_temp_free_vec(t1);
> }
>
> /* Expand OPSZ bytes worth of two-vector operands and an immediate operand
> @@ -1088,7 +1104,8 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
> * that e.g. size == 80 would be expanded with 2x32 + 1x16.
> */
> some = QEMU_ALIGN_DOWN(oprsz, 32);
> - expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, g->fniv);
> + expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
> + g->load_dest, g->fniv);
> if (some == oprsz) {
> break;
> }
> @@ -1098,17 +1115,19 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
> maxsz -= some;
> /* fallthru */
> case TCG_TYPE_V128:
> - expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv);
> + expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
> + g->load_dest, g->fniv);
> break;
> case TCG_TYPE_V64:
> - expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv);
> + expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
> + g->load_dest, g->fniv);
> break;
>
> case 0:
> if (g->fni8 && check_size_impl(oprsz, 8)) {
> - expand_2_i64(dofs, aofs, oprsz, g->fni8);
> + expand_2_i64(dofs, aofs, oprsz, g->load_dest, g->fni8);
> } else if (g->fni4 && check_size_impl(oprsz, 4)) {
> - expand_2_i32(dofs, aofs, oprsz, g->fni4);
> + expand_2_i32(dofs, aofs, oprsz, g->load_dest, g->fni4);
> } else {
> assert(g->fno != NULL);
> tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno);
--
Alex Bennée
next prev parent reply other threads:[~2020-04-23 9:38 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-22 1:16 [PATCH v2 00/36] tcg 5.1 omnibus patch set Richard Henderson
2020-04-22 1:16 ` [PATCH v2 01/36] tcg: Add tcg_gen_gvec_dup_imm Richard Henderson
2020-04-22 1:16 ` [PATCH v2 02/36] target/s390x: Use tcg_gen_gvec_dup_imm Richard Henderson
2020-04-22 1:16 ` [PATCH v2 03/36] target/ppc: " Richard Henderson
2020-04-22 1:16 ` [PATCH v2 04/36] target/arm: " Richard Henderson
2020-04-22 1:16 ` [PATCH v2 05/36] tcg: Use tcg_gen_gvec_dup_imm in logical simplifications Richard Henderson
2020-04-22 1:16 ` [PATCH v2 06/36] tcg: Remove tcg_gen_gvec_dup{8,16,32,64}i Richard Henderson
2020-04-22 1:16 ` [PATCH v2 07/36] tcg: Add tcg_gen_gvec_dup_tl Richard Henderson
2020-04-22 1:16 ` [PATCH v2 08/36] tcg: Improve vector tail clearing Richard Henderson
2020-04-22 1:16 ` [PATCH v2 09/36] tcg: Consolidate 3 bits into enum TCGTempKind Richard Henderson
2020-04-22 11:25 ` Alex Bennée
2020-04-22 19:58 ` Aleksandar Markovic
2020-04-23 9:00 ` Philippe Mathieu-Daudé
2020-04-23 15:40 ` Richard Henderson
2020-04-23 17:24 ` Daniel P. Berrangé
2020-04-23 23:11 ` Richard Henderson
2020-04-24 9:08 ` Daniel P. Berrangé
2020-04-22 1:16 ` [PATCH v2 10/36] tcg: Add temp_readonly Richard Henderson
2020-04-22 11:26 ` Alex Bennée
2020-04-22 1:16 ` [PATCH v2 11/36] tcg: Introduce TYPE_CONST temporaries Richard Henderson
2020-04-22 15:17 ` Alex Bennée
2020-04-22 16:55 ` Richard Henderson
2020-04-22 1:16 ` [PATCH v2 12/36] tcg: Use tcg_constant_i32 with icount expander Richard Henderson
2020-04-22 15:40 ` Alex Bennée
2020-04-22 1:16 ` [PATCH v2 13/36] tcg: Use tcg_constant_{i32, i64} with tcg int expanders Richard Henderson
2020-04-22 16:18 ` [PATCH v2 13/36] tcg: Use tcg_constant_{i32,i64} " Alex Bennée
2020-04-22 17:02 ` Richard Henderson
2020-04-22 17:57 ` Alex Bennée
2020-04-22 20:04 ` Alex Bennée
2020-04-23 23:13 ` Richard Henderson
2020-04-24 13:23 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 14/36] tcg: Use tcg_constant_{i32, vec} with tcg vec expanders Richard Henderson
2020-04-22 17:00 ` [PATCH v2 14/36] tcg: Use tcg_constant_{i32,vec} " Alex Bennée
2020-04-22 1:17 ` [PATCH v2 15/36] tcg: Use tcg_constant_{i32,i64} with tcg plugins Richard Henderson
2020-04-22 17:18 ` [PATCH v2 15/36] tcg: Use tcg_constant_{i32, i64} " Alex Bennée
2020-04-22 1:17 ` [PATCH v2 16/36] tcg: Rename struct tcg_temp_info to TempOptInfo Richard Henderson
2020-04-22 17:19 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 17/36] tcg/optimize: Adjust TempOptInfo allocation Richard Henderson
2020-04-22 17:53 ` Alex Bennée
2020-04-22 18:28 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 18/36] tcg/optimize: Use tcg_constant_internal with constant folding Richard Henderson
2020-04-22 18:28 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 19/36] tcg/tci: Add special tci_movi_{i32,i64} opcodes Richard Henderson
2020-04-22 19:02 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 20/36] tcg: Remove movi and dupi opcodes Richard Henderson
2020-04-22 9:12 ` Aleksandar Markovic
2020-04-22 19:03 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 21/36] tcg: Use tcg_out_dupi_vec from temp_load Richard Henderson
2020-04-22 19:28 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 22/36] tcg: Increase tcg_out_dupi_vec immediate to int64_t Richard Henderson
2020-04-22 19:33 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 23/36] tcg: Add tcg_reg_alloc_dup2 Richard Henderson
2020-04-22 19:40 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 24/36] tcg/i386: Use tcg_constant_vec with tcg vec expanders Richard Henderson
2020-04-22 19:43 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 25/36] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec Richard Henderson
2020-04-23 9:11 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 26/36] tcg: Add load_dest parameter to GVecGen2 Richard Henderson
2020-04-23 9:37 ` Alex Bennée [this message]
2020-04-22 1:17 ` [PATCH v2 27/36] tcg: Fix integral argument type to tcg_gen_rot[rl]i_i{32, 64} Richard Henderson
2020-04-22 10:19 ` Philippe Mathieu-Daudé
2020-04-23 9:38 ` [PATCH v2 27/36] tcg: Fix integral argument type to tcg_gen_rot[rl]i_i{32,64} Alex Bennée
2020-04-22 1:17 ` [PATCH v2 28/36] tcg: Implement gvec support for rotate by immediate Richard Henderson
2020-04-23 13:28 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 29/36] tcg: Implement gvec support for rotate by vector Richard Henderson
2020-04-23 13:41 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 30/36] tcg: Remove expansion to shift by vector from do_shifts Richard Henderson
2020-04-22 1:17 ` [PATCH v2 31/36] tcg: Implement gvec support for rotate by scalar Richard Henderson
2020-04-23 13:46 ` Alex Bennée
2020-04-22 1:17 ` [PATCH v2 32/36] tcg/i386: Implement INDEX_op_rotl[is]_vec Richard Henderson
2020-04-22 1:17 ` [PATCH v2 33/36] tcg/aarch64: Implement INDEX_op_rotli_vec Richard Henderson
2020-04-22 1:17 ` [PATCH v2 34/36] tcg/ppc: Implement INDEX_op_rot[lr]v_vec Richard Henderson
2020-04-22 1:17 ` [PATCH v2 35/36] target/ppc: Use tcg_gen_gvec_rotlv Richard Henderson
2020-04-22 1:17 ` [PATCH v2 36/36] target/s390x: Use tcg_gen_gvec_rotl{i,s,v} Richard Henderson
2020-04-23 13:50 ` [PATCH v2 00/36] tcg 5.1 omnibus patch set Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87a732bl12.fsf@linaro.org \
--to=alex.bennee@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).