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Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > This promotes constants to full-fledged temporaries, which are then > hashed so we have only a single copy across the TB. If an opcode > requires forcing one into a register, then we will only do this > once -- at least until the register is killed, e.g. by a function call. > > While this is probably an modest improvement for integer code, it is > significant for SVE vector code. In particular, where a generator functi= on > loads a constant for the operation, and then the generator function is > called N times for the N x 128-bit vector. Previously we'd be loading > up the same constant N times and now we do so only once. > > The existing tcg_const_{type}() functions are unchanged, allocating > a new temporary and initializing it. The constant propagation pass > of the optimizer will generally remove the temporary when it turns > out not to be modified further. > > This adds new tcg_constant_{type}() functions which produce a read-only > temporary containing the constant which need not be freed. I have > updated the generic expanders to take advantage of this, but have not > touched the target front ends. > > This also, in the end, allows the complete removal of the tcg opcodes > that create a constant: INDEX_op_movi_{i32,i64} and INDEX_op_dupi_vec. > Loading of constants into hard registers is completely controlled by > the register allocator. > > > r~ > > > Richard Henderson (16): > tcg: Add temp_readonly The series failed to apply at the first patch. Should it be based on any other patches? --=20 Alex Benn=C3=A9e