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X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Richard Henderson writes: > This is part of a reorganization to the set of mmu_idx. > The EL1&0 regime is the only one that uses 2-stage translation. > Spelling out Stage avoids confusion with Secure. > > Signed-off-by: Richard Henderson > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 97677f8482..a34accec20 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -2992,7 +2992,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint= 64_t value, > bool take_exc =3D false; >=20=20 > if (fi.s1ptw && current_el =3D=3D 1 && !arm_is_secure(env) > - && (mmu_idx =3D=3D ARMMMUIdx_S1NSE1 || mmu_idx =3D=3D ARMMMU= Idx_S1NSE0)) { > + && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 > + || mmu_idx =3D=3D ARMMMUIdx_Stage1_E0)) { Personal nit: I think ||\nfoo =3D=3D scans more nicely as it lines up but maybe that's just me. Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e