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X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com, amarkovic@wavecomp.com, philmd@redhat.com, Qemu Devel , aurelien@aurel32.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Mikhail Abakumov writes: > From: Mikhail Abakumov Hmm the email got truncated here. > > This patch add xml files with gdb registers for mips. > > Signed-off-by: Mikhail Abakumov > --- > configure | 3 ++ > gdb-xml/mips-core.xml | 84 +++++++++++++++++++++++++++++++++++++++++ > gdb-xml/mips64-core.xml | 84 > +++++++++++++++++++++++++++++++++++++++++ Otherwise for the configure/xml: Acked-by: Alex Benn=C3=A9e I assume the changes will go in via a MIPS tree. > target/mips/cpu.c | 11 ++++++ > 4 files changed, 182 insertions(+) > create mode 100644 gdb-xml/mips-core.xml > create mode 100644 gdb-xml/mips64-core.xml > > diff --git a/configure b/configure > index 8f8446f52b..5bb2c62194 100755 > --- a/configure > +++ b/configure > @@ -7466,12 +7466,14 @@ case "$target_name" in > mips|mipsel) > mttcg=3D"yes" > TARGET_ARCH=3Dmips > + gdb_xml_files=3D"mips-core.xml" > echo "TARGET_ABI_MIPSO32=3Dy" >> $config_target_mak > ;; > mipsn32|mipsn32el) > mttcg=3D"yes" > TARGET_ARCH=3Dmips64 > TARGET_BASE_ARCH=3Dmips > + gdb_xml_files=3D"mips64-core.xml" > echo "TARGET_ABI_MIPSN32=3Dy" >> $config_target_mak > echo "TARGET_ABI32=3Dy" >> $config_target_mak > ;; > @@ -7479,6 +7481,7 @@ case "$target_name" in > mttcg=3D"yes" > TARGET_ARCH=3Dmips64 > TARGET_BASE_ARCH=3Dmips > + gdb_xml_files=3D"mips64-core.xml" > echo "TARGET_ABI_MIPSN64=3Dy" >> $config_target_mak > ;; > moxie) > diff --git a/gdb-xml/mips-core.xml b/gdb-xml/mips-core.xml > new file mode 100644 > index 0000000000..a46b2993eb > --- /dev/null > +++ b/gdb-xml/mips-core.xml > @@ -0,0 +1,84 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/gdb-xml/mips64-core.xml b/gdb-xml/mips64-core.xml > new file mode 100644 > index 0000000000..cc1a15ad56 > --- /dev/null > +++ b/gdb-xml/mips64-core.xml > @@ -0,0 +1,84 @@ > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > diff --git a/target/mips/cpu.c b/target/mips/cpu.c > index bbcf7ca463..014f1db59e 100644 > --- a/target/mips/cpu.c > +++ b/target/mips/cpu.c > @@ -181,6 +181,11 @@ static ObjectClass *mips_cpu_class_by_name(const > char *cpu_model) > return oc; > } > > +static gchar *mips_gdb_arch_name(CPUState *cs) > +{ > + return g_strdup("mips"); > +} > + > static void mips_cpu_class_init(ObjectClass *c, void *data) > { > MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c); > @@ -213,6 +218,12 @@ static void mips_cpu_class_init(ObjectClass *c, > void *data) > cc->tlb_fill =3D mips_cpu_tlb_fill; > #endif > > + cc->gdb_arch_name =3D mips_gdb_arch_name; > +#ifdef TARGET_MIPS64 > + cc->gdb_core_xml_file =3D "mips64-core.xml"; > +#else > + cc->gdb_core_xml_file =3D "mips-core.xml"; > +#endif > cc->gdb_num_core_regs =3D 73; > cc->gdb_stop_before_watchpoint =3D true; > } -- Alex Benn=C3=A9e