From: "Alex Bennée" <alex.bennee@linaro.org>
To: Alistair Francis <alistair.francis@xilinx.com>
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org,
qemu-devel@nongnu.org, crosthwaitepeter@gmail.com,
edgar.iglesias@gmail.com, afaerber@suse.de,
fred.konrad@greensocs.com
Subject: Re: [Qemu-devel] [PATCH v5 01/15] bitops: Add MAKE_64BIT_MASK macro
Date: Tue, 22 Mar 2016 15:26:46 +0000 [thread overview]
Message-ID: <87a8lqsfd5.fsf@linaro.org> (raw)
In-Reply-To: <912f91bdbccf665fddd51b186027a3ae702d768a.1457470980.git.alistair.francis@xilinx.com>
Alistair Francis <alistair.francis@xilinx.com> writes:
> Add a macro that creates a 64bit value which has length number of ones
> shifted acrros by the value of shift.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> V5:
> - Re-write to a 64-bit mask instead of ONES()
> - Re-order this patch in the series
>
> include/qemu/bitops.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
> index 755fdd1..3c45791 100644
> --- a/include/qemu/bitops.h
> +++ b/include/qemu/bitops.h
> @@ -24,6 +24,9 @@
> #define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
> #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
>
> +#define MAKE_64BIT_MASK(shift, length) \
> + (((1ull << (length)) - 1) << shift)
> +
> /**
> * set_bit - Set a bit in memory
> * @nr: the bit to set
--
Alex Bennée
next prev parent reply other threads:[~2016-03-22 15:26 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-08 21:06 [Qemu-devel] [PATCH v5 00/15] data-driven device registers Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 01/15] bitops: Add MAKE_64BIT_MASK macro Alistair Francis
2016-03-22 15:26 ` Alex Bennée [this message]
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 02/15] register: Add Register API Alistair Francis
2016-03-22 16:28 ` Alex Bennée
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 03/15] register: Add Memory API glue Alistair Francis
2016-03-22 16:56 ` Alex Bennée
2016-03-24 23:03 ` Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 04/15] register: Add support for decoding information Alistair Francis
2016-03-22 17:42 ` Alex Bennée
2016-03-24 23:17 ` Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 05/15] register: Define REG and FIELD macros Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 06/15] register: QOMify Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 07/15] register: Add block initialise helper Alistair Francis
2016-03-22 17:11 ` Alex Bennée
2016-03-24 23:28 ` Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 08/15] dma: Add Xilinx Zynq devcfg device model Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 09/15] xilinx_zynq: Connect devcfg to the Zynq machine model Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 10/15] qdev: Define qdev_get_gpio_out Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 11/15] qdev: Add qdev_pass_all_gpios API Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 12/15] irq: Add opaque setter routine Alistair Francis
2016-03-08 21:07 ` [Qemu-devel] [PATCH v5 13/15] register: Add GPIO API Alistair Francis
2016-03-08 21:07 ` [Qemu-devel] [PATCH v5 14/15] misc: Introduce ZynqMP IOU SLCR Alistair Francis
2016-03-22 17:44 ` [Qemu-devel] [PATCH v5 00/15] data-driven device registers Alex Bennée
2016-03-24 23:43 ` Alistair Francis
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