From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: "Richard W.M. Jones" <rjones@redhat.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, pbonzini@redhat.com
Subject: Re: [PATCH v2] target/riscv: Use a direct cast for better performance
Date: Mon, 9 Oct 2023 12:23:55 +0200 [thread overview]
Message-ID: <87bc3f73-f3d5-0431-6339-6d8c978b89c4@linaro.org> (raw)
In-Reply-To: <20231008215147.3362612-2-rjones@redhat.com>
Hi Richard,
On 8/10/23 23:50, Richard W.M. Jones wrote:
> RISCV_CPU(cs) uses a checked cast. When QOM cast debugging is enabled
> this adds about 5% total overhead when emulating RV64 on x86-64 host.
>
> Using a RISC-V guest with 16 vCPUs, 16 GB of guest RAM, virtio-blk
> disk. The guest has a copy of the qemu source tree. The test
> involves compiling the qemu source tree with 'make clean; time make -j16'.
>
> Before making this change the compile step took 449 & 447 seconds over
> two consecutive runs.
>
> After making this change, 428 & 422 seconds.
>
> The saving is about 5%.
>
> Thanks: Paolo Bonzini
> Signed-off-by: Richard W.M. Jones <rjones@redhat.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu_helper.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 3a02079290..479d9863ae 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -66,7 +66,11 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> uint64_t *cs_base, uint32_t *pflags)
> {
> CPUState *cs = env_cpu(env);
> - RISCVCPU *cpu = RISCV_CPU(cs);
You might want to use:
RISCVCPU *cpu = env_archcpu(env);
Other occurences in target/riscv/internals.h.
> + /*
> + * Using the checked cast RISCV_CPU(cs) imposes ~ 5% overhead when
> + * QOM cast debugging is enabled, so use a direct cast instead.
> + */
> + RISCVCPU *cpu = (RISCVCPU *)cs;
> RISCVExtStatus fs, vs;
> uint32_t flags = 0;
>
next prev parent reply other threads:[~2023-10-09 10:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-08 21:50 [PATCH v2] target/riscv: Use a direct cast for better performance Richard W.M. Jones
2023-10-08 21:50 ` Richard W.M. Jones
2023-10-09 10:23 ` Philippe Mathieu-Daudé [this message]
2023-10-09 12:36 ` LIU Zhiwei
2023-10-09 12:53 ` Richard W.M. Jones
2023-10-09 12:58 ` LIU Zhiwei
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