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Thu, 23 Jun 2022 14:06:39 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 07E44BE056; Thu, 23 Jun 2022 14:06:39 +0000 (GMT) Received: from localhost (unknown [9.160.47.189]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTPS; Thu, 23 Jun 2022 14:06:38 +0000 (GMT) From: Fabiano Rosas To: =?utf-8?Q?V=C3=ADctor?= Colombo , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, danielhb413@gmail.com, david@gibson.dropbear.id.au, groug@kaod.org, richard.henderson@linaro.org, victor.colombo@eldorado.org.br, matheus.ferst@eldorado.org.br, lucas.araujo@eldorado.org.br, lucas.coutinho@eldorado.org.br, leandro.lupori@eldorado.org.br Subject: Re: [PATCH] target/ppc: Change FPSCR_* to follow POWER ISA numbering convention In-Reply-To: <20220622193203.127698-1-victor.colombo@eldorado.org.br> References: <20220622193203.127698-1-victor.colombo@eldorado.org.br> Date: Thu, 23 Jun 2022 11:06:36 -0300 Message-ID: <87bkuja2z7.fsf@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: y_ulPNFzczYTxhsxBARHY3j_3gJ50yxz X-Proofpoint-GUID: k80NB8hjCcQUuv9rEDAy1OvflHOw37Iv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-06-23_06,2022-06-23_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 lowpriorityscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 spamscore=0 phishscore=0 mlxlogscore=637 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206230055 Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" V=C3=ADctor Colombo writes: > FPSCR_* bit values in QEMU are in the 'inverted' order from what Power > ISA defines (e.g. FPSCR.FI is bit 46 but is defined as 17 in cpu.h). > Now that PPC_BIT_NR macro was introduced to fix this situation for the > MSR bits, we can use it for the FPSCR bits too. > > Also, adjust the comments to make then fit in 80 columns > > Signed-off-by: V=C3=ADctor Colombo Apart form the typo below. Reviewed-by: Fabiano Rosas > --- > target/ppc/cpu.h | 72 ++++++++++++++++++++++++------------------------ > 1 file changed, 36 insertions(+), 36 deletions(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 6d78078f37..c78f64cced 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -694,42 +694,42 @@ enum { > +#define FPSCR_DRN2 PPC_BIT_NR(29) /* Decimal Floating-Point rounding c= trl. */ > +#define FPSCR_DRN1 PPC_BIT_NR(30) /* Decimal Floating-Point rounding c= trl. */ > +#define FPSCR_DRN0 PPC_BIT_NR(31) /* Decimal Floating-Point rounding c= trl. */ > +#define FPSCR_FX PPC_BIT_NR(32) /* Floating-point exception summary = */ > +#define FPSCR_FEX PPC_BIT_NR(33) /* Floating-point enabled exception = summ.*/ > +#define FPSCR_VX PPC_BIT_NR(34) /* Floating-point invalid op. excp. = summ.*/ > +#define FPSCR_OX PPC_BIT_NR(35) /* Floating-point overflow exception= */ > +#define FPSCR_UX PPC_BIT_NR(36) /* Floating-point underflow exceptio= */ exception > +#define FPSCR_ZX PPC_BIT_NR(37) /* Floating-point zero divide except= ion */ > +#define FPSCR_XX PPC_BIT_NR(38) /* Floating-point inexact exception = */ > +#define FPSCR_VXSNAN PPC_BIT_NR(39) /* Floating-point invalid op. excp (= sNan)*/ > +#define FPSCR_VXISI PPC_BIT_NR(40) /* Floating-point invalid op. excp (= inf) */ > +#define FPSCR_VXIDI PPC_BIT_NR(41) /* Floating-point invalid op. excp (= inf) */ > +#define FPSCR_VXZDZ PPC_BIT_NR(42) /* Floating-point invalid op. excp (= zero)*/ > +#define FPSCR_VXIMZ PPC_BIT_NR(43) /* Floating-point invalid op. excp (= inf) */ > +#define FPSCR_VXVC PPC_BIT_NR(44) /* Floating-point invalid op. excp (= comp)*/ > +#define FPSCR_FR PPC_BIT_NR(45) /* Floating-point fraction rounded = */ > +#define FPSCR_FI PPC_BIT_NR(46) /* Floating-point fraction inexact = */ > +#define FPSCR_C PPC_BIT_NR(47) /* Floating-point result class descr= iptor*/ > +#define FPSCR_FL PPC_BIT_NR(48) /* Floating-point less than or negat= ive */ > +#define FPSCR_FG PPC_BIT_NR(49) /* Floating-point greater than or ne= g. */ > +#define FPSCR_FE PPC_BIT_NR(50) /* Floating-point equal or zero = */ > +#define FPSCR_FU PPC_BIT_NR(51) /* Floating-point unordered or NaN = */ > +#define FPSCR_FPCC PPC_BIT_NR(51) /* Floating-point condition code = */ > +#define FPSCR_FPRF PPC_BIT_NR(51) /* Floating-point result flags = */ > +#define FPSCR_VXSOFT PPC_BIT_NR(53) /* Floating-point invalid op. excp (= soft)*/ > +#define FPSCR_VXSQRT PPC_BIT_NR(54) /* Floating-point invalid op. excp (= sqrt)*/ > +#define FPSCR_VXCVI PPC_BIT_NR(55) /* Floating-point invalid op. excp (= int) */ > +#define FPSCR_VE PPC_BIT_NR(56) /* Floating-point invalid op. excp e= nable*/ > +#define FPSCR_OE PPC_BIT_NR(57) /* Floating-point overflow excp. ena= ble */ > +#define FPSCR_UE PPC_BIT_NR(58) /* Floating-point underflow excp. en= able */ > +#define FPSCR_ZE PPC_BIT_NR(59) /* Floating-point zero divide excp e= nable*/ > +#define FPSCR_XE PPC_BIT_NR(60) /* Floating-point inexact excp. enab= le */ > +#define FPSCR_NI PPC_BIT_NR(61) /* Floating-point non-IEEE mode = */ > +#define FPSCR_RN1 PPC_BIT_NR(62) > +#define FPSCR_RN0 PPC_BIT_NR(63) /* Floating-point rounding control = */ > /* Invalid operation exception summary */ > #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ > (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \