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From: Fabiano Rosas <farosas@linux.ibm.com>
To: "Cédric Le Goater" <clg@kaod.org>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
	richard.henderson@linaro.org, david@gibson.dropbear.id.au
Subject: Re: [PATCH 5/9] target/ppc: Use ppc_interrupts_little_endian in powerpc_excp
Date: Tue, 04 Jan 2022 11:11:17 -0300	[thread overview]
Message-ID: <87bl0rh9q2.fsf@linux.ibm.com> (raw)
In-Reply-To: <ca700ead-7cf1-6d8c-12f6-9d03b547d517@kaod.org>

Cédric Le Goater <clg@kaod.org> writes:

> On 1/3/22 23:07, Fabiano Rosas wrote:
>> The ppc_interrupts_little_endian function is suitable for determining
>> the endianness of interrupts for all Book3S CPUs.
>> 
>> (I'm keeping the MSR check for the rest of the CPUs, but it will go
>> away in the next patch.)
>> 
>> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
>> ---
>>   target/ppc/excp_helper.c | 21 ++-------------------
>>   1 file changed, 2 insertions(+), 19 deletions(-)
>> 
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 0dbadc5d07..5d31940426 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -760,25 +760,8 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp)
>>        * CPU, the HV mode, etc...
>>        */
>>   #ifdef TARGET_PPC64
>> -    if (excp_model == POWERPC_EXCP_POWER7) {
>> -        if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) {
>> -            new_msr |= (target_ulong)1 << MSR_LE;
>> -        }
>> -    } else if (excp_model == POWERPC_EXCP_POWER8) {
>> -        if (new_msr & MSR_HVB) {
>> -            if (env->spr[SPR_HID0] & HID0_HILE) {
>> -                new_msr |= (target_ulong)1 << MSR_LE;
>> -            }
>> -        } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
>> -            new_msr |= (target_ulong)1 << MSR_LE;
>> -        }
>> -    } else if (excp_model == POWERPC_EXCP_POWER9 ||
>> -               excp_model == POWERPC_EXCP_POWER10) {
>> -        if (new_msr & MSR_HVB) {
>> -            if (env->spr[SPR_HID0] & HID0_POWER9_HILE) {
>> -                new_msr |= (target_ulong)1 << MSR_LE;
>> -            }
>> -        } else if (env->spr[SPR_LPCR] & LPCR_ILE) {
>> +    if (excp_model >= POWERPC_EXCP_970) {
>
> why include POWERPC_EXCP_970 ? These CPUs do not support Little Endian.
>

Because the 970 exception model covers POWER5P as well which has ILE.

And looking at cpu_init.c, POWER5 uses a bunch of 970 functions. And
POWER7 uses the POWER5 ones. So we kind of have a dependency chain
there. That is why I'm always handling ">= 970" as "books".


  reply	other threads:[~2022-01-04 14:12 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-03 22:07 [PATCH 0/9] target/ppc: powerpc_excp improvements (2/n) Fabiano Rosas
2022-01-03 22:07 ` [PATCH 1/9] target/ppc: powerpc_excp: Extract software TLB logging into a function Fabiano Rosas
2022-01-04  9:32   ` Cédric Le Goater
2022-01-03 22:07 ` [PATCH 2/9] target/ppc: powerpc_excp: Keep 60x soft MMU logs active Fabiano Rosas
2022-01-04  9:33   ` Cédric Le Goater
2022-01-03 22:07 ` [PATCH 3/9] target/ppc: powerpc_excp: Group unimplemented exceptions Fabiano Rosas
2022-01-04  9:39   ` Cédric Le Goater
2022-01-03 22:07 ` [PATCH 4/9] target/ppc: Add HV support to ppc_interrupts_little_endian Fabiano Rosas
2022-01-03 22:07 ` [PATCH 5/9] target/ppc: Use ppc_interrupts_little_endian in powerpc_excp Fabiano Rosas
2022-01-04 10:09   ` Cédric Le Goater
2022-01-04 14:11     ` Fabiano Rosas [this message]
2022-01-04 17:30       ` Cédric Le Goater
2022-01-03 22:07 ` [PATCH 6/9] target/ppc: powerpc_excp: Preserve MSR_LE bit Fabiano Rosas
2022-01-04 20:51   ` Fabiano Rosas
2022-01-03 22:07 ` [PATCH 7/9] target/ppc: powerpc_excp: Move ILE setting into a function Fabiano Rosas
2022-01-03 22:07 ` [PATCH 8/9] target/ppc: powerpc_excp: Move AIL under a Book3s block Fabiano Rosas
2022-01-03 22:07 ` [PATCH 9/9] target/ppc: Introduce a wrapper for powerpc_excp Fabiano Rosas

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