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Thu, 15 Apr 2021 07:32:43 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id h17sm3647085wru.67.2021.04.15.07.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Apr 2021 07:32:42 -0700 (PDT) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AC4F41FF7E; Thu, 15 Apr 2021 15:32:41 +0100 (BST) References: <20210218094706.23038-1-alex.bennee@linaro.org> <20210218094706.23038-19-alex.bennee@linaro.org> User-agent: mu4e 1.5.11; emacs 28.0.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Peter Maydell Subject: Re: [PULL 18/23] accel/tcg: re-factor non-RAM execution code Date: Thu, 15 Apr 2021 15:31:00 +0100 In-reply-to: Message-ID: <87blaflit2.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --8<---------------cut here---------------start------------->8--- Peter Maydell writes: > On Thu, 15 Apr 2021 at 14:18, Peter Maydell wr= ote: >> >> On Thu, 18 Feb 2021 at 09:47, Alex Benn=C3=A9e = wrote: >> > >> > There is no real need to use CF_NOCACHE here. As long as the TB isn't >> > linked to other TBs or included in the QHT or jump cache then it will >> > only get executed once. >> > >> > Signed-off-by: Alex Benn=C3=A9e >> > Reviewed-by: Richard Henderson >> > Message-Id: <20210213130325.14781-19-alex.bennee@linaro.org> >> >> Hi; I've just noticed that this commit seems to break the case of: >> * execution of code not from a RAM block >> * when icount is enabled >> * and an instruction is an IO insn that triggers io-recompile >> >> because: >> >> > @@ -2097,6 +2086,17 @@ TranslationBlock *tb_gen_code(CPUState *cpu, >> > tb_reset_jump(tb, 1); >> > } >> > >> > + /* >> > + * If the TB is not associated with a physical RAM page then >> > + * it must be a temporary one-insn TB, and we have nothing to do >> > + * except fill in the page_addr[] fields. Return early before >> > + * attempting to link to other TBs or add to the lookup table. >> > + */ >> > + if (phys_pc =3D=3D -1) { >> > + tb->page_addr[0] =3D tb->page_addr[1] =3D -1; >> > + return tb; >> > + } >> >> we used to fall through here, which meant we called >> tcg_tb_insert(tb). No we no longer do. That's bad, because >> cpu_io_recompile() does: >> >> tb =3D tcg_tb_lookup(retaddr); >> if (!tb) { >> cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=3D%p", >> (void *)retaddr); >> } >> >> and since it can no longer find the TB, QEMU aborts. > > Adding the tcg_tb_insert() call to the early exit path: > > diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c > index ba6ab09790e..6014285e4dc 100644 > --- a/accel/tcg/translate-all.c > +++ b/accel/tcg/translate-all.c > @@ -2081,6 +2081,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, > */ > if (phys_pc =3D=3D -1) { > tb->page_addr[0] =3D tb->page_addr[1] =3D -1; > + tcg_tb_insert(tb); > return tb; > } > > seems to fix my test case, but I don't know enough about the new > design here to know if that has undesirable side effects. No we don't want to do that as the comment says above. However as it's a single instruction block it can do IO so could you try this instead please: --8<---------------cut here---------------start------------->8--- accel/tcg: avoid re-translating one-shot instructions By definition a single instruction is capable of being an IO instruction. This avoids a problem of triggering a cpu_io_recompile on a non-cached translation which would only do exactly this anyway. Signed-off-by: Alex Benn=C3=A9e 1 file changed, 1 insertion(+), 1 deletion(-) accel/tcg/translate-all.c | 2 +- modified accel/tcg/translate-all.c @@ -1863,7 +1863,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 if (phys_pc =3D=3D -1) { /* Generate a one-shot TB with 1 insn in it */ - cflags =3D (cflags & ~CF_COUNT_MASK) | 1; + cflags =3D (cflags & ~CF_COUNT_MASK) | CF_LAST_IO | 1; } =20 max_insns =3D cflags & CF_COUNT_MASK; --8<---------------cut here---------------end--------------->8--- --=20 Alex Benn=C3=A9e