From: "Alex Bennée" <alex.bennee@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org,
Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org
Subject: Re: [PATCH 1/2] arm.risu: Correct VLDR/VSTR U=0 patterns
Date: Mon, 14 Sep 2020 14:42:03 +0100 [thread overview]
Message-ID: <87bli81nmc.fsf@linaro.org> (raw)
In-Reply-To: <20200901162046.32670-2-peter.maydell@linaro.org>
Peter Maydell <peter.maydell@linaro.org> writes:
> Correct the VLDR and VSTR patterns, which claimed to be setting U=0
> but in fact left it identical to the U=1 pattern due to a
> cut-and-paste error.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Somehow the pre-generated test binaries I have from Alex have
> U=0 insns in them -- I suspect this got fixed locally but never
> made it upstream ?
Hmm my current set of aarch32 test patterns have U=1 throughout. So if
it did get fixed locally it also got lost.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
next prev parent reply other threads:[~2020-09-14 13:45 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-01 16:20 [RISU PATCH 0/2] arm.risu: two minor fixes Peter Maydell
2020-09-01 16:20 ` [PATCH 1/2] arm.risu: Correct VLDR/VSTR U=0 patterns Peter Maydell
2020-09-14 13:42 ` Alex Bennée [this message]
2020-09-14 13:44 ` Peter Maydell
2020-09-01 16:20 ` [PATCH 2/2] arm.risu: Fix typo in VCVT_B_TT pattern name Peter Maydell
2020-09-14 13:42 ` Alex Bennée
2020-09-10 19:54 ` [RISU PATCH 0/2] arm.risu: two minor fixes Peter Maydell
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