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X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , "open list:RISC-V TCG CPUs" , Sagar Karandikar , Bastian Koppelmann , qemu-devel@nongnu.org, robhenry@microsoft.com, aaron@os.amperecomputing.com, cota@braap.org, Palmer Dabbelt , kuhn.chenqun@huawei.com, Peter Puhov Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Robert Foley writes: > Hi, > On Fri, 7 Feb 2020 at 10:01, Alex Benn=C3=A9e wr= ote: >> -static void decode_RV32_64C0(DisasContext *ctx) >> +static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode) >> { >> - uint8_t funct3 =3D extract32(ctx->opcode, 13, 3); >> - uint8_t rd_rs2 =3D GET_C_RS2S(ctx->opcode); >> - uint8_t rs1s =3D GET_C_RS1S(ctx->opcode); >> + uint8_t funct3 =3D extract32(opcode, 13, 3); > > We noticed that a uint16_t opcode is passed into this function and > then passed on to extract32(). > This is a minor point, but the extract32() will validate the start and > length values passed in according to 32 bits, not 16 bits. > static inline uint32_t extract32(uint32_t value, int start, int length) > { > assert(start >=3D 0 && length > 0 && length <=3D 32 - start); > Since we have an extract32() and extract64(), maybe we could add an > extract16() and use it here? Yeah - I did consider if it would be worth adding a extract16 helper. There are a fair number of places in the code base where uint16_t is silently promoted to a uint32_t (and a couple where it is downcast). I guess 16 bit instruction words are common enough we should support them in the utils. --=20 Alex Benn=C3=A9e