From: "Alex Bennée" <alex.bennee@linaro.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, "Aurelien Jarno" <aurelien@aurel32.net>,
"Fam Zheng" <famz@redhat.com>,
"Gerd Hoffmann" <kraxel@redhat.com>,
"Laurent Vivier" <laurent@vivier.eu>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Richard Henderson" <rth@twiddle.net>,
"Riku Voipio" <riku.voipio@iki.fi>,
"Yongbok Kim" <yongbok.kim@mips.com>,
"Aleksandar Markovic" <aleksandar.markovic@mips.com>,
"Goran Ferenc" <goran.ferenc@mips.com>,
"Miodrag Dinic" <miodrag.dinic@mips.com>,
"Petar Jovanovic" <petar.jovanovic@mips.com>,
"Raghu Gandham" <raghu.gandham@mips.com>
Subject: Re: [Qemu-devel] [PATCH v2 3/6] hw/mips_int: hold BQL for all interrupt requests
Date: Wed, 04 Apr 2018 14:44:57 +0100 [thread overview]
Message-ID: <87bmezcch2.fsf@linaro.org> (raw)
In-Reply-To: <6b04fe74-2a84-63d8-5519-fd2fdfe3f4a3@redhat.com>
Paolo Bonzini <pbonzini@redhat.com> writes:
> On 04/04/2018 12:23, Alex Bennée wrote:
>>
>>> From: Aleksandar Markovic <aleksandar.markovic@mips.com>
>>>
>>> Make sure BQL is held for all interrupt requests.
>>>
>>> For MTTCG-enabled configurations, handling soft and hard interrupts
>>> between vCPUs must be properly locked. By acquiring BQL, make sure
>>> all paths triggering an IRQ are synchronized.
>>>
>>> Signed-off-by: Miodrag Dinic <miodrag.dinic@mips.com>
>>> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
>
> Is this actually necessary? What paths are not taking the lock?
Helpers functions have to manually take the lock. AIUI from this patch
the if (locked) dance allows a single function to be used which may
trigger an IRQ from both helpers (no automatic locking) and hw emulation
(locked by default).
>
> Thanks,
>
> Paolo
--
Alex Bennée
next prev parent reply other threads:[~2018-04-04 13:45 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-22 18:31 [Qemu-devel] [PATCH v2 0/6] target-mips: support MTTCG feature Aleksandar Markovic
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 1/6] target/mips: compare virtual addresses in LL/SC sequence Aleksandar Markovic
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 2/6] target/mips: reimplement SC instruction emulation and use cmpxchg Aleksandar Markovic
2018-02-22 22:33 ` Emilio G. Cota
2018-02-22 22:39 ` Emilio G. Cota
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 3/6] hw/mips_int: hold BQL for all interrupt requests Aleksandar Markovic
2018-04-04 10:23 ` Alex Bennée
2018-04-04 11:23 ` Paolo Bonzini
2018-04-04 13:44 ` Alex Bennée [this message]
2018-04-04 14:42 ` Paolo Bonzini
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 4/6] target/mips: hold BQL in mips_vpe_wake() Aleksandar Markovic
2018-04-04 10:24 ` Alex Bennée
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 5/6] hw/mips_cpc: kick a VP when putting it into Run state Aleksandar Markovic
2018-04-04 10:25 ` Alex Bennée
2018-02-22 18:31 ` [Qemu-devel] [PATCH v2 6/6] target/mips: introduce MTTCG-enabled builds Aleksandar Markovic
2018-04-04 10:25 ` Alex Bennée
2018-04-04 10:27 ` [Qemu-devel] [PATCH v2 0/6] target-mips: support MTTCG feature Alex Bennée
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