From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52863) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrmFp-0004ZS-Rl for qemu-devel@nongnu.org; Tue, 03 Jun 2014 06:47:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WrmFk-0002Vb-PT for qemu-devel@nongnu.org; Tue, 03 Jun 2014 06:47:41 -0400 Received: from static.88-198-71-155.clients.your-server.de ([88.198.71.155]:46352 helo=socrates.bennee.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WrmFk-0002VH-Jn for qemu-devel@nongnu.org; Tue, 03 Jun 2014 06:47:36 -0400 References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> <1401434911-26992-16-git-send-email-edgar.iglesias@gmail.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= In-reply-to: <1401434911-26992-16-git-send-email-edgar.iglesias@gmail.com> Date: Tue, 03 Jun 2014 11:47:35 +0100 Message-ID: <87bnuas20o.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v1 15/16] target-arm: Add IRQ and FIQ routing to EL2 and 3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Edgar E. Iglesias" Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, rob.herring@linaro.org, aggelerf@ethz.ch, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, christoffer.dall@linaro.org, rth@twiddle.net Edgar E. Iglesias writes: > From: "Edgar E. Iglesias" > > Signed-off-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 10 ++++++++++ > target-arm/helper.c | 16 ++++++++++++++++ > 2 files changed, 26 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index b3631f2..d15e8d2 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -1133,6 +1133,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) > CPUARMState *env = cs->env_ptr; > unsigned int cur_el = arm_current_pl(env); > unsigned int target_el = arm_excp_target_el(cs, excp_idx); > + /* FIXME: Use actual secure state. */ > + bool secure = false; Again FIXME? > > /* Don't take exceptions if they target a lower EL. */ > if (cur_el > target_el) { > @@ -1141,8 +1143,16 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) > > switch (excp_idx) { > case EXCP_FIQ: > + if (!secure && cur_el < 2 && target_el == 2 > + && (env->cp15.hcr_el2 & HCR_FMO)) { > + return true; > + } > return !(env->daif & PSTATE_F); > case EXCP_IRQ: > + if (!secure && cur_el < 2 && target_el == 2 > + && (env->cp15.hcr_el2 & HCR_IMO)) { > + return true; > + } > return ((IS_M(env) && env->regs[15] < 0xfffffff0) > || !(env->daif & PSTATE_I)); Hmm identical but subtly different tests may cause later trip ups. > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 35091ea..649476b 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3304,6 +3304,22 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) > target_el = 2; > } > break; > + case EXCP_IRQ: > + if (!secure && (env->cp15.hcr_el2 & HCR_IMO)) { > + target_el = 2; > + } > + if (env->cp15.scr_el3 & SCR_IRQ) { > + target_el = 3; > + } > + break; > + case EXCP_FIQ: > + if (!secure && (env->cp15.hcr_el2 & HCR_FMO)) { > + target_el = 2; > + } > + if (env->cp15.scr_el3 & SCR_FIQ) { > + target_el = 3; > + } > + break; I wonder if it's possible to make the common logic more common while keeping the differences? > } > return target_el; > } -- Alex Bennée