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From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set
Date: Sat, 27 Jan 2024 13:09:13 +1000	[thread overview]
Message-ID: <87c249b0-8f08-40e6-91c1-1d3c970b567a@linaro.org> (raw)
In-Reply-To: <20240125134304.1470404-1-peter.maydell@linaro.org>

On 1/25/24 23:43, Peter Maydell wrote:
> In kernel commit 5d5b4e8c2d9ec ("arm64/sve: Report FEAT_SVE_B16B16 to
> userspace") Linux added ID_AA64ZFR0_el1.B16B16 to the set of ID
> register fields which it exposes to userspace.  Update our
> exported_bits mask to include this.
> 
> (This doesn't yet change any behaviour for us, because we don't yet
> have any CPUs that implement this feature, which is part of SVE2.)
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> This is a loose end from last year: in commit 5f7b71fb99dc I
> updated our mask values to match the kernel, and when I was
> doing that I noticed that the kernel had forgotten to add
> B16B16 to its report-to-userspace list when adding support
> for that architectural feature. Now the kernel has fixed its
> side, we can update again to match it.
> ---
>   target/arm/helper.c         | 1 +
>   tests/tcg/aarch64/sysregs.c | 2 +-
>   2 files changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


      reply	other threads:[~2024-01-27  3:10 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-25 13:43 [PATCH] target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set Peter Maydell
2024-01-27  3:09 ` Richard Henderson [this message]

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