From: "Cédric Le Goater" <clg@kaod.org>
To: Fabiano Rosas <farosas@linux.ibm.com>, <qemu-devel@nongnu.org>
Cc: richard.henderson@linaro.org, danielhb413@gmail.com,
mark.cave-ayland@ilande.co.uk, qemu-ppc@nongnu.org,
openbios@openbios.org, david@gibson.dropbear.id.au
Subject: Re: [RFC PATCH v2 1/4] target/ppc: Disable software TLB for the 7450 family
Date: Fri, 3 Dec 2021 13:56:03 +0100 [thread overview]
Message-ID: <87cce1e1-9869-f9c8-f0e3-a4063c8fdade@kaod.org> (raw)
In-Reply-To: <20211130230123.781844-2-farosas@linux.ibm.com>
On 12/1/21 00:01, Fabiano Rosas wrote:
> (Applies to 7441, 7445, 7450, 7451, 7455, 7457, 7447 and 7447a)*
>
> We have since 2011 [1] been unable to run OpenBIOS in the 7450s and
> have not heard of any other software that is used with those CPUs in
> QEMU. A current discussion [2] shows that the 7450 software TLB is
> unsupported in Linux 5.15, FreeBSD 13, MacOS9, MacOSX and MorphOS
> 3.15. With no known support in firmware or OS, this means that no code
> for any of the 7450 CPUs is ever ran in QEMU.
>
> Since the implementation in QEMU of the 7400 MMU is the same as the
> 7450, except for the software TLB vs. hardware TLB search, this patch
> changes all 7450 cpus to the 7400 MMU model. This has the practical
> effect of disabling the software TLB feature while keeping other
> aspects of address translation working as expected.
>
> This allow us to run software on the 7450 family again.
>
> *- note that the 7448 is currently aliased in QEMU for a 7400, so it
> is unaffected by this change.
but it has a 7448 PVR. May be that's why we see an issue when
booting Linux.
> 1- https://bugs.launchpad.net/qemu/+bug/812398
> https://gitlab.com/qemu-project/qemu/-/issues/86
>
> 2- https://lists.nongnu.org/archive/html/qemu-ppc/2021-11/msg00289.html
> message id: 20211119134431.406753-1-farosas@linux.ibm.com
>
> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> target/ppc/cpu_init.c | 25 ++++++++++---------------
> 1 file changed, 10 insertions(+), 15 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index 6695985e9b..509df35d09 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -5932,7 +5932,6 @@ static void init_proc_7440(CPUPPCState *env)
> 0x00000000);
> /* Memory management */
> register_low_BATs(env);
> - register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -5956,7 +5955,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
> PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
> PPC_MEM_SYNC | PPC_MEM_EIEIO |
> PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> - PPC_MEM_TLBIA | PPC_74xx_TLB |
> + PPC_MEM_TLBIA |
> PPC_SEGMENT | PPC_EXTERN |
> PPC_ALTIVEC;
> pcc->msr_mask = (1ull << MSR_VR) |
> @@ -5976,7 +5975,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
> (1ull << MSR_PMM) |
> (1ull << MSR_RI) |
> (1ull << MSR_LE);
> - pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
> + pcc->mmu_model = POWERPC_MMU_32B;
> pcc->excp_model = POWERPC_EXCP_74xx;
> pcc->bus_model = PPC_FLAGS_INPUT_6xx;
> pcc->bfd_mach = bfd_mach_ppc_7400;
> @@ -6067,7 +6066,6 @@ static void init_proc_7450(CPUPPCState *env)
> 0x00000000);
> /* Memory management */
> register_low_BATs(env);
> - register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6091,7 +6089,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
> PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
> PPC_MEM_SYNC | PPC_MEM_EIEIO |
> PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> - PPC_MEM_TLBIA | PPC_74xx_TLB |
> + PPC_MEM_TLBIA |
> PPC_SEGMENT | PPC_EXTERN |
> PPC_ALTIVEC;
> pcc->msr_mask = (1ull << MSR_VR) |
> @@ -6111,7 +6109,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
> (1ull << MSR_PMM) |
> (1ull << MSR_RI) |
> (1ull << MSR_LE);
> - pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
> + pcc->mmu_model = POWERPC_MMU_32B;
> pcc->excp_model = POWERPC_EXCP_74xx;
> pcc->bus_model = PPC_FLAGS_INPUT_6xx;
> pcc->bfd_mach = bfd_mach_ppc_7400;
> @@ -6205,7 +6203,6 @@ static void init_proc_7445(CPUPPCState *env)
> /* Memory management */
> register_low_BATs(env);
> register_high_BATs(env);
> - register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6229,7 +6226,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
> PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
> PPC_MEM_SYNC | PPC_MEM_EIEIO |
> PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> - PPC_MEM_TLBIA | PPC_74xx_TLB |
> + PPC_MEM_TLBIA |
> PPC_SEGMENT | PPC_EXTERN |
> PPC_ALTIVEC;
> pcc->msr_mask = (1ull << MSR_VR) |
> @@ -6249,7 +6246,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
> (1ull << MSR_PMM) |
> (1ull << MSR_RI) |
> (1ull << MSR_LE);
> - pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
> + pcc->mmu_model = POWERPC_MMU_32B;
> pcc->excp_model = POWERPC_EXCP_74xx;
> pcc->bus_model = PPC_FLAGS_INPUT_6xx;
> pcc->bfd_mach = bfd_mach_ppc_7400;
> @@ -6345,7 +6342,6 @@ static void init_proc_7455(CPUPPCState *env)
> /* Memory management */
> register_low_BATs(env);
> register_high_BATs(env);
> - register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6369,7 +6365,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
> PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
> PPC_MEM_SYNC | PPC_MEM_EIEIO |
> PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> - PPC_MEM_TLBIA | PPC_74xx_TLB |
> + PPC_MEM_TLBIA |
> PPC_SEGMENT | PPC_EXTERN |
> PPC_ALTIVEC;
> pcc->msr_mask = (1ull << MSR_VR) |
> @@ -6389,7 +6385,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
> (1ull << MSR_PMM) |
> (1ull << MSR_RI) |
> (1ull << MSR_LE);
> - pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
> + pcc->mmu_model = POWERPC_MMU_32B;
> pcc->excp_model = POWERPC_EXCP_74xx;
> pcc->bus_model = PPC_FLAGS_INPUT_6xx;
> pcc->bfd_mach = bfd_mach_ppc_7400;
> @@ -6509,7 +6505,6 @@ static void init_proc_7457(CPUPPCState *env)
> /* Memory management */
> register_low_BATs(env);
> register_high_BATs(env);
> - register_74xx_soft_tlb(env, 128, 2);
> init_excp_7450(env);
> env->dcache_line_size = 32;
> env->icache_line_size = 32;
> @@ -6533,7 +6528,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
> PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
> PPC_MEM_SYNC | PPC_MEM_EIEIO |
> PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
> - PPC_MEM_TLBIA | PPC_74xx_TLB |
> + PPC_MEM_TLBIA |
> PPC_SEGMENT | PPC_EXTERN |
> PPC_ALTIVEC;
> pcc->msr_mask = (1ull << MSR_VR) |
> @@ -6553,7 +6548,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
> (1ull << MSR_PMM) |
> (1ull << MSR_RI) |
> (1ull << MSR_LE);
> - pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
> + pcc->mmu_model = POWERPC_MMU_32B;
> pcc->excp_model = POWERPC_EXCP_74xx;
> pcc->bus_model = PPC_FLAGS_INPUT_6xx;
> pcc->bfd_mach = bfd_mach_ppc_7400;
>
next prev parent reply other threads:[~2021-12-03 12:57 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-30 23:01 [RFC PATCH v2 0/4] QEMU/openbios: PPC Software TLB support in the G4 family Fabiano Rosas
2021-11-30 23:01 ` [RFC PATCH v2 1/4] target/ppc: Disable software TLB for the 7450 family Fabiano Rosas
2021-12-03 12:56 ` Cédric Le Goater [this message]
2021-11-30 23:01 ` [RFC PATCH v2 2/4] target/ppc: Disable unused facilities in the e600 CPU Fabiano Rosas
2021-12-03 12:56 ` Cédric Le Goater
2021-11-30 23:01 ` [RFC PATCH v2 3/4] target/ppc: Remove the software TLB model of 7450 CPUs Fabiano Rosas
2021-12-03 12:57 ` Cédric Le Goater
2021-11-30 23:01 ` [RFC PATCH v2 4/4] tests/avocado: ppc: Add smoke tests for MPC7400 and MPC7450 families Fabiano Rosas
2021-12-01 10:09 ` Cédric Le Goater
2021-12-15 16:47 ` [RFC PATCH v2 0/4] QEMU/openbios: PPC Software TLB support in the G4 family Cédric Le Goater
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