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Wed, 26 Feb 2025 01:07:17 -0800 (PST) Received: from draig.lan ([185.126.160.109]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43aba532d7asm13929045e9.13.2025.02.26.01.07.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Feb 2025 01:07:17 -0800 (PST) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 94F305F87C; Wed, 26 Feb 2025 09:07:16 +0000 (GMT) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Peter Maydell Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org Subject: Re: [PATCH v3 5/9] target/arm: Refactor handling of timer offset for direct register accesses In-Reply-To: <20250204125009.2281315-6-peter.maydell@linaro.org> (Peter Maydell's message of "Tue, 4 Feb 2025 12:50:05 +0000") References: <20250204125009.2281315-1-peter.maydell@linaro.org> <20250204125009.2281315-6-peter.maydell@linaro.org> User-Agent: mu4e 1.12.8; emacs 29.4 Date: Wed, 26 Feb 2025 09:07:16 +0000 Message-ID: <87cyf53whn.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Peter Maydell writes: > When reading or writing the timer registers, sometimes we need to > apply one of the timer offsets. Specifically, this happens for > direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and > their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0). It > also applies for direct reads and writes of the CNT*_TVAL_EL* > registers that provide the 32-bit downcounting view of each timer. > > We currently do this with duplicated code in gt_tval_read() and > gt_tval_write() and a special-case in gt_virt_cnt_read() and > gt_cnt_read(). Refactor this so that we handle it all in a single > function gt_direct_access_timer_offset(), to parallel how we handle > the offset for indirect accesses. > > The call in the WFIT helper previously to gt_virt_cnt_offset() is > now to gt_direct_access_timer_offset(); this is the correct > behaviour, but it's not immediately obvious that it shouldn't be > considered an indirect access, so we add an explanatory comment. > > This commit should make no behavioural changes. > > (Cc to stable because the following bugfix commit will > depend on this one.) > > Cc: qemu-stable@nongnu.org > Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro