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Wed, 02 Oct 2024 08:35:07 -0700 (PDT) Received: from draig (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id C55FE5F780; Wed, 2 Oct 2024 16:35:06 +0100 (BST) From: =?utf-8?Q?Alex_Benn=C3=A9e?= To: Helge Deller Cc: Richard Henderson , qemu-devel@nongnu.org, linux-parisc@vger.kernel.org Subject: Re: {PATCH] accel/tcg: Fix CPU specific unaligned behaviour In-Reply-To: (Helge Deller's message of "Wed, 2 Oct 2024 04:37:10 +0200") References: User-Agent: mu4e 1.12.6; emacs 29.4 Date: Wed, 02 Oct 2024 16:35:06 +0100 Message-ID: <87cykimsb9.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Helge Deller writes: > When the emulated CPU reads or writes to a memory location > a) for which no read/write permissions exists, *and* > b) the access happens unaligned (non-natural alignment), > then the CPU should either > - trigger a permission fault, or > - trigger an unalign access fault. > > In the current code the alignment check happens before the memory > permission checks, so only unalignment faults will be triggered. > > This behaviour breaks the emulation of the PARISC architecture, where the= CPU > does a memory verification first. The behaviour can be tested with the te= stcase > from the bugzilla report. > > Add the necessary code to allow PARISC and possibly other architectures to > trigger a memory fault instead. > > Signed-off-by: Helge Deller > Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=3D219339 > > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index 117b516739..dd1da358fb 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -1684,6 +1684,26 @@ static void mmu_watch_or_dirty(CPUState *cpu, MMUL= ookupPageData *data, > data->flags =3D flags; > } >=20=20 > +/* when accessing unreadable memory unaligned, will the CPU issue > + * a alignment trap or a memory access trap ? */ > +#ifdef TARGET_HPPA > +# define CPU_ALIGNMENT_CHECK_AFTER_MEMCHECK 1 > +#else > +# define CPU_ALIGNMENT_CHECK_AFTER_MEMCHECK 0 > +#endif I'm pretty certain we don't want to be introducing per-guest hacks into the core cputlb.c code when we are aiming to make it a compile once object. I guess the real question is where could we put this flag? My gut says we should expand the MO_ALIGN bits in MemOp to express the precedence or not of the alignment check in relation to permissions. > + > +static void mmu_check_alignment(CPUState *cpu, vaddr addr, > + uintptr_t ra, MMUAccessType type, MMULookupLocals= *l) > +{ > + unsigned a_bits; > + > + /* Handle CPU specific unaligned behaviour */ > + a_bits =3D get_alignment_bits(l->memop); > + if (addr & ((1 << a_bits) - 1)) { > + cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); > + } > +} > + > /** > * mmu_lookup: translate page(s) > * @cpu: generic cpu state > @@ -1699,7 +1719,6 @@ static void mmu_watch_or_dirty(CPUState *cpu, MMULo= okupPageData *data, > static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, > uintptr_t ra, MMUAccessType type, MMULookupLocals= *l) > { > - unsigned a_bits; > bool crosspage; > int flags; >=20=20 > @@ -1708,10 +1727,8 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, = MemOpIdx oi, >=20=20 > tcg_debug_assert(l->mmu_idx < NB_MMU_MODES); >=20=20 > - /* Handle CPU specific unaligned behaviour */ > - a_bits =3D get_alignment_bits(l->memop); > - if (addr & ((1 << a_bits) - 1)) { > - cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); > + if (!CPU_ALIGNMENT_CHECK_AFTER_MEMCHECK) { Then this would be something like: if (!(memop & MO_ALIGN_PP)) or something > + mmu_check_alignment(cpu, addr, ra, type, l); > } >=20=20 > l->page[0].addr =3D addr; > @@ -1760,6 +1777,10 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, = MemOpIdx oi, > tcg_debug_assert((flags & TLB_BSWAP) =3D=3D 0); > } >=20=20 > + if (CPU_ALIGNMENT_CHECK_AFTER_MEMCHECK) { > + mmu_check_alignment(cpu, addr, ra, type, l); > + } > + > /* > * This alignment check differs from the one above, in that this is > * based on the atomicity of the operation. The intended use case is --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro